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https://github.com/c64scene-ar/llvm-6502.git
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b3f912b510
r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
227 lines
4.7 KiB
LLVM
227 lines
4.7 KiB
LLVM
; Test 32-bit ANDs in which the second operand is constant.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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; ANDs with 1 can use NILF.
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define i32 @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: nilf %r2, 1
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; CHECK: br %r14
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%and = and i32 %a, 1
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ret i32 %and
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}
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; ...but RISBLG is available as a three-address form.
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define i32 @f2(i32 %a, i32 %b) {
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; CHECK-LABEL: f2:
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; CHECK: risblg %r2, %r3, 31, 159, 0
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; CHECK: br %r14
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%and = and i32 %b, 1
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ret i32 %and
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}
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; ...same for 4.
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define i32 @f3(i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: risblg %r2, %r3, 29, 157, 0
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; CHECK: br %r14
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%and = and i32 %b, 4
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ret i32 %and
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}
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; ANDs with 5 must use NILF.
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define i32 @f4(i32 %a) {
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; CHECK-LABEL: f4:
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; CHECK: nilf %r2, 5
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; CHECK: br %r14
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%and = and i32 %a, 5
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ret i32 %and
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}
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; ...a single RISBLG isn't enough.
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define i32 @f5(i32 %a, i32 %b) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: risb
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; CHECK: br %r14
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%and = and i32 %b, 5
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ret i32 %and
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}
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; Check the highest 16-bit constant that must be handled by NILF.
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define i32 @f6(i32 %a) {
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; CHECK-LABEL: f6:
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; CHECK: nilf %r2, 65533
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; CHECK: br %r14
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%and = and i32 %a, 65533
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ret i32 %and
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}
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; ...a single RISBLG isn't enough.
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define i32 @f7(i32 %a, i32 %b) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: risb
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; CHECK: br %r14
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%and = and i32 %b, 65533
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ret i32 %and
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}
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; Check the next highest value, which can use NILF.
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define i32 @f8(i32 %a) {
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; CHECK-LABEL: f8:
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; CHECK: nilf %r2, 65534
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; CHECK: br %r14
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%and = and i32 %a, 65534
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ret i32 %and
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}
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; ...although the three-address case should use RISBLG.
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define i32 @f9(i32 %a, i32 %b) {
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; CHECK-LABEL: f9:
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; CHECK: risblg %r2, %r3, 16, 158, 0
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; CHECK: br %r14
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%and = and i32 %b, 65534
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ret i32 %and
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}
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; ANDs of 0xffff are zero extensions from i16.
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define i32 @f10(i32 %a, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: llhr %r2, %r3
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; CHECK: br %r14
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%and = and i32 %b, 65535
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ret i32 %and
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}
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; Check the next value up, which must again use NILF.
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define i32 @f11(i32 %a) {
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; CHECK-LABEL: f11:
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; CHECK: nilf %r2, 65536
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; CHECK: br %r14
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%and = and i32 %a, 65536
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ret i32 %and
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}
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; ...but the three-address case can use RISBLG.
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define i32 @f12(i32 %a, i32 %b) {
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; CHECK-LABEL: f12:
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; CHECK: risblg %r2, %r3, 15, 143, 0
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; CHECK: br %r14
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%and = and i32 %b, 65536
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ret i32 %and
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}
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; Check the lowest useful NILH value.
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define i32 @f13(i32 %a) {
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; CHECK-LABEL: f13:
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; CHECK: nilh %r2, 1
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; CHECK: br %r14
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%and = and i32 %a, 131071
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ret i32 %and
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}
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; ...but RISBLG is OK in the three-address case.
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define i32 @f14(i32 %a, i32 %b) {
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; CHECK-LABEL: f14:
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; CHECK: risblg %r2, %r3, 15, 159, 0
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; CHECK: br %r14
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%and = and i32 %b, 131071
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ret i32 %and
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}
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; Check the highest useful NILF value.
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define i32 @f15(i32 %a) {
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; CHECK-LABEL: f15:
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; CHECK: nilf %r2, 4294901758
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; CHECK: br %r14
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%and = and i32 %a, -65538
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ret i32 %and
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}
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; Check the next value up, which is the highest useful NILH value.
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define i32 @f16(i32 %a) {
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; CHECK-LABEL: f16:
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; CHECK: nilh %r2, 65534
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; CHECK: br %r14
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%and = and i32 %a, -65537
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ret i32 %and
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}
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; Check the next value up, which is the first useful NILL value.
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define i32 @f17(i32 %a) {
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; CHECK-LABEL: f17:
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; CHECK: nill %r2, 0
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; CHECK: br %r14
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%and = and i32 %a, -65536
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ret i32 %and
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}
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; ...although the three-address case should use RISBLG.
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define i32 @f18(i32 %a, i32 %b) {
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; CHECK-LABEL: f18:
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; CHECK: risblg %r2, %r3, 0, 143, 0
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; CHECK: br %r14
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%and = and i32 %b, -65536
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ret i32 %and
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}
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; Check the next value up again, which can still use NILL.
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define i32 @f19(i32 %a) {
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; CHECK-LABEL: f19:
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; CHECK: nill %r2, 1
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; CHECK: br %r14
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%and = and i32 %a, -65535
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ret i32 %and
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}
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; Check the next value up again, which cannot use RISBLG.
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define i32 @f20(i32 %a, i32 %b) {
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; CHECK-LABEL: f20:
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; CHECK-NOT: risb
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; CHECK: br %r14
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%and = and i32 %b, -65534
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ret i32 %and
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}
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; Check the last useful mask, which can use NILL.
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define i32 @f21(i32 %a) {
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; CHECK-LABEL: f21:
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; CHECK: nill %r2, 65534
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; CHECK: br %r14
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%and = and i32 %a, -2
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ret i32 %and
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}
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; ...or RISBLG for the three-address case.
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define i32 @f22(i32 %a, i32 %b) {
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; CHECK-LABEL: f22:
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; CHECK: risblg %r2, %r3, 0, 158, 0
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; CHECK: br %r14
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%and = and i32 %b, -2
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ret i32 %and
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}
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; Test that RISBLG can be used when inserting a non-wraparound mask
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; into another register.
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define i64 @f23(i64 %a, i32 %b) {
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; CHECK-LABEL: f23:
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; CHECK: risblg %r2, %r3, 30, 158, 0
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; CHECK: br %r14
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%and1 = and i64 %a, -4294967296
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%and2 = and i32 %b, 2
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%ext = zext i32 %and2 to i64
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%or = or i64 %and1, %ext
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ret i64 %or
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}
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; ...and when inserting a wrap-around mask.
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define i64 @f24(i64 %a, i32 %b) {
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; CHECK-LABEL: f24:
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; CHECK: risblg %r2, %r3, 30, 156
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; CHECK: br %r14
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%and1 = and i64 %a, -4294967296
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%and2 = and i32 %b, -5
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%ext = zext i32 %and2 to i64
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%or = or i64 %and1, %ext
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ret i64 %or
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}
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