Pete Cooper 9fb69672d6 [X86 fast-isel] Constrain the index reg class to not include SP. ... The index reg on instructions with complex address modes is a GPR64_NOSP. Constrain it to appease the machine verifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236557 91177308-0d34-0410-b5e6-96231b3b80d8		2015-05-05 23:41:53 +00:00
..
Analysis	Update BasicAliasAnalysis to understand that nothing aliases with undef values.	2015-05-05 18:10:49 +00:00
AsmParser
Bitcode
CodeGen	[SelectionDAG] Make an argument optional in RFV::getCopyToRegs. NFC.	2015-05-05 23:06:57 +00:00
DebugInfo	Fix build.	2015-05-01 20:33:10 +00:00
ExecutionEngine	[Orc] Reapply r236465 with fixes for the MSVC bots.	2015-05-05 17:37:18 +00:00
Fuzzer	[lib/Fuzzer] on crash print the contents of the crashy input as base64	2015-05-05 21:59:51 +00:00
IR	[opaque pointer type] Track explicit GEP pointee type through in-memory IR	2015-05-05 18:03:48 +00:00
IRReader
LineEditor
Linker
LTO
MC	Respect object format choice on Darwin	2015-05-04 20:03:01 +00:00
Object
Option	Option parsing: properly handle flag aliases for joined options (PR23394)	2015-05-04 18:00:13 +00:00
Passes
ProfileData
Support	[SystemZ] Add z13 vector facility and MC support	2015-05-05 19:23:40 +00:00
TableGen	[TableGen] Replace 'static_cast' with 'cast'.	2015-05-04 01:35:42 +00:00
Target	[X86 fast-isel] Constrain the index reg class to not include SP.	2015-05-05 23:41:53 +00:00
Transforms	[Inliner] Discard empty COMDAT groups	2015-05-05 20:14:22 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile