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https://github.com/c64scene-ar/llvm-6502.git
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52a261b3c1
passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
665 lines
21 KiB
TableGen
665 lines
21 KiB
TableGen
//===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Cell SPU Instruction Operands:
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//===----------------------------------------------------------------------===//
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// TO_IMM32 - Convert an i8/i16 to i32.
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def TO_IMM32 : SDNodeXForm<imm, [{
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return getI32Imm(N->getZExtValue());
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}]>;
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// TO_IMM16 - Convert an i8/i32 to i16.
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def TO_IMM16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i16);
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}]>;
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def LO16 : SDNodeXForm<imm, [{
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unsigned val = N->getZExtValue();
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// Transformation function: get the low 16 bits.
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return getI32Imm(val & 0xffff);
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}]>;
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def LO16_vec : SDNodeXForm<scalar_to_vector, [{
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SDValue OpVal(0, 0);
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// Transformation function: get the low 16 bit immediate from a build_vector
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// node.
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assert(N->getOpcode() == ISD::BUILD_VECTOR
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&& "LO16_vec got something other than a BUILD_VECTOR");
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// Get first constant operand...
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for (unsigned i = 0, e = N->getNumOperands();
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OpVal.getNode() == 0 && i != e; ++i) {
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if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
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if (OpVal.getNode() == 0)
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OpVal = N->getOperand(i);
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}
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assert(OpVal.getNode() != 0 && "LO16_vec did not locate a <defined> node");
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ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
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return getI32Imm((unsigned)CN->getZExtValue() & 0xffff);
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}]>;
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// Transform an immediate, returning the high 16 bits shifted down:
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def HI16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getZExtValue() >> 16);
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}]>;
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// Transformation function: shift the high 16 bit immediate from a build_vector
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// node into the low 16 bits, and return a 16-bit constant.
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def HI16_vec : SDNodeXForm<scalar_to_vector, [{
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SDValue OpVal(0, 0);
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assert(N->getOpcode() == ISD::BUILD_VECTOR
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&& "HI16_vec got something other than a BUILD_VECTOR");
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// Get first constant operand...
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for (unsigned i = 0, e = N->getNumOperands();
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OpVal.getNode() == 0 && i != e; ++i) {
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if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
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if (OpVal.getNode() == 0)
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OpVal = N->getOperand(i);
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}
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assert(OpVal.getNode() != 0 && "HI16_vec did not locate a <defined> node");
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ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
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return getI32Imm((unsigned)CN->getZExtValue() >> 16);
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}]>;
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// simm7 predicate - True if the immediate fits in an 7-bit signed
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// field.
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def simm7: PatLeaf<(imm), [{
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int sextVal = int(N->getSExtValue());
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return (sextVal >= -64 && sextVal <= 63);
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}]>;
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// uimm7 predicate - True if the immediate fits in an 7-bit unsigned
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// field.
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def uimm7: PatLeaf<(imm), [{
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return (N->getZExtValue() <= 0x7f);
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}]>;
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// immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
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// field.
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def immSExt8 : PatLeaf<(imm), [{
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int Value = int(N->getSExtValue());
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return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
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}]>;
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// immU8: immediate, unsigned 8-bit quantity
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def immU8 : PatLeaf<(imm), [{
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return (N->getZExtValue() <= 0xff);
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}]>;
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// i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
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// extended field. Used by RI10Form instructions like 'ldq'.
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def i32ImmSExt10 : PatLeaf<(imm), [{
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return isI32IntS10Immediate(N);
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}]>;
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// i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
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// field. Used by RI10Form instructions like 'ldq'.
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def i32ImmUns10 : PatLeaf<(imm), [{
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return isI32IntU10Immediate(N);
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}]>;
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// i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
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// extended field. Used by RI10Form instructions like 'ldq'.
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def i16ImmSExt10 : PatLeaf<(imm), [{
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return isI16IntS10Immediate(N);
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}]>;
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// i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
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// value. Used by RI10Form instructions.
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def i16ImmUns10 : PatLeaf<(imm), [{
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return isI16IntU10Immediate(N);
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}]>;
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def immSExt16 : PatLeaf<(imm), [{
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// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
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// field.
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short Ignored;
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return isIntS16Immediate(N, Ignored);
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}]>;
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def immZExt16 : PatLeaf<(imm), [{
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// immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
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// field.
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return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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}], LO16>;
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def immU16 : PatLeaf<(imm), [{
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// immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
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return (uint64_t)N->getZExtValue() == (N->getZExtValue() & 0xffff);
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}]>;
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def imm18 : PatLeaf<(imm), [{
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// imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
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int Value = (int) N->getZExtValue();
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return ((Value & ((1 << 19) - 1)) == Value);
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}]>;
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def lo16 : PatLeaf<(imm), [{
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// lo16 predicate - returns true if the immediate has all zeros in the
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// low order bits and is a 32-bit constant:
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if (N->getValueType(0) == MVT::i32) {
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uint32_t val = N->getZExtValue();
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return ((val & 0x0000ffff) == val);
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}
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return false;
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}], LO16>;
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def hi16 : PatLeaf<(imm), [{
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// hi16 predicate - returns true if the immediate has all zeros in the
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// low order bits and is a 32-bit constant:
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if (N->getValueType(0) == MVT::i32) {
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uint32_t val = uint32_t(N->getZExtValue());
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return ((val & 0xffff0000) == val);
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} else if (N->getValueType(0) == MVT::i64) {
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uint64_t val = N->getZExtValue();
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return ((val & 0xffff0000ULL) == val);
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}
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return false;
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}], HI16>;
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def bitshift : PatLeaf<(imm), [{
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// bitshift predicate - returns true if 0 < imm <= 7 for SHLQBII
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// (shift left quadword by bits immediate)
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int64_t Val = N->getZExtValue();
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return (Val > 0 && Val <= 7);
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}]>;
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//===----------------------------------------------------------------------===//
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// Floating point operands:
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//===----------------------------------------------------------------------===//
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// Transform a float, returning the high 16 bits shifted down, as if
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// the float was really an unsigned integer:
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def HI16_f32 : SDNodeXForm<fpimm, [{
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float fval = N->getValueAPF().convertToFloat();
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return getI32Imm(FloatToBits(fval) >> 16);
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}]>;
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// Transformation function on floats: get the low 16 bits as if the float was
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// an unsigned integer.
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def LO16_f32 : SDNodeXForm<fpimm, [{
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float fval = N->getValueAPF().convertToFloat();
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return getI32Imm(FloatToBits(fval) & 0xffff);
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}]>;
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def FPimm_sext16 : SDNodeXForm<fpimm, [{
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float fval = N->getValueAPF().convertToFloat();
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return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16));
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}]>;
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def FPimm_u18 : SDNodeXForm<fpimm, [{
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float fval = N->getValueAPF().convertToFloat();
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return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
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}]>;
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def fpimmSExt16 : PatLeaf<(fpimm), [{
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short Ignored;
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return isFPS16Immediate(N, Ignored);
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}], FPimm_sext16>;
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// Does the SFP constant only have upp 16 bits set?
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def hi16_f32 : PatLeaf<(fpimm), [{
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if (N->getValueType(0) == MVT::f32) {
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uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
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return ((val & 0xffff0000) == val);
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}
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return false;
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}], HI16_f32>;
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// Does the SFP constant fit into 18 bits?
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def fpimm18 : PatLeaf<(fpimm), [{
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if (N->getValueType(0) == MVT::f32) {
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uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
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return ((Value & ((1 << 19) - 1)) == Value);
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}
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return false;
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}], FPimm_u18>;
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//===----------------------------------------------------------------------===//
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// 64-bit operands (TODO):
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// build_vector operands:
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//===----------------------------------------------------------------------===//
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// v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended
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// immediate constant load for v16i8 vectors. N.B.: The incoming constant has
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// to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
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def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
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}]>;
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// v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
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// load, works in conjunction with its transform function. N.B.: This relies the
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// incoming constant being a 16-bit quantity, where the upper and lower bytes
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// are EXACTLY the same (e.g., 0x2a2a)
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def v16i8SExt8Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
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}], v16i8SExt8Imm_xform>;
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// v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
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// immediate constant load for v16i8 vectors. N.B.: The incoming constant has
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// to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
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def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
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}]>;
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// v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
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// load, works in conjunction with its transform function. N.B.: This relies the
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// incoming constant being a 16-bit quantity, where the upper and lower bytes
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// are EXACTLY the same (e.g., 0x2a2a)
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def v16i8U8Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
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}], v16i8U8Imm_xform>;
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// v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
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// immediate constant load for v8i16 vectors.
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def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
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}]>;
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// v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
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// load, works in conjunction with its transform function.
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def v8i16SExt8Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
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}], v8i16SExt8Imm_xform>;
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// v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
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// immediate constant load for v8i16 vectors.
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def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
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}]>;
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// v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
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// load, works in conjunction with its transform function.
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def v8i16SExt10Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
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}], v8i16SExt10Imm_xform>;
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// v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
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// immediate constant load for v8i16 vectors.
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def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
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}]>;
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// v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
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// load, works in conjunction with its transform function.
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def v8i16Uns10Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
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}], v8i16Uns10Imm_xform>;
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// v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
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// immediate constant load for v8i16 vectors.
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def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
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}]>;
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// v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
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// load, works in conjunction with its transform function.
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def v8i16SExt16Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
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}], v8i16Uns16Imm_xform>;
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// v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
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// immediate constant load for v4i32 vectors.
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def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
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}]>;
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// v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
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// load, works in conjunction with its transform function.
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def v4i32SExt10Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
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}], v4i32SExt10Imm_xform>;
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// v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
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// immediate constant load for v4i32 vectors.
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def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
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}]>;
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// v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
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// load, works in conjunction with its transform function.
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def v4i32Uns10Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
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}], v4i32Uns10Imm_xform>;
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// v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
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// immediate constant load for v4i32 vectors.
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def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
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}]>;
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// v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
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// load, works in conjunction with its transform function.
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def v4i32SExt16Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
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}], v4i32SExt16Imm_xform>;
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// v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
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// immediate constant load for v4i32 vectors.
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def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
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}]>;
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// v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
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// works in conjunction with its transform function.
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def v4i32Uns18Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0;
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}], v4i32Uns18Imm_xform>;
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// ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
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// load.
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def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
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return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
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}]>;
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/// immILHUvec: Predicate test for a ILHU constant vector.
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def immILHUvec: PatLeaf<(build_vector), [{
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return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0;
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}], ILHUvec_get_imm>;
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// Catch-all for any other i32 vector constants
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def v4i32_get_imm: SDNodeXForm<build_vector, [{
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return SPU::get_v4i32_imm(N, *CurDAG);
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}]>;
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def v4i32Imm: PatLeaf<(build_vector), [{
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return SPU::get_v4i32_imm(N, *CurDAG).getNode() != 0;
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}], v4i32_get_imm>;
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// v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
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// immediate constant load for v2i64 vectors.
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def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
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}]>;
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// v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
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// load, works in conjunction with its transform function.
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def v2i64SExt10Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0;
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}], v2i64SExt10Imm_xform>;
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// v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
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// immediate constant load for v2i64 vectors.
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def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
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return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
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}]>;
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// v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
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// load, works in conjunction with its transform function.
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def v2i64SExt16Imm: PatLeaf<(build_vector), [{
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return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0;
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}], v2i64SExt16Imm_xform>;
|
|
|
|
// v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
|
|
// immediate constant load for v2i64 vectors.
|
|
def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
|
|
return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
|
|
}]>;
|
|
|
|
// v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
|
|
// works in conjunction with its transform function.
|
|
def v2i64Uns18Imm: PatLeaf<(build_vector), [{
|
|
return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0;
|
|
}], v2i64Uns18Imm_xform>;
|
|
|
|
/// immILHUvec: Predicate test for a ILHU constant vector.
|
|
def immILHUvec_i64: PatLeaf<(build_vector), [{
|
|
return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0;
|
|
}], ILHUvec_get_imm>;
|
|
|
|
// Catch-all for any other i32 vector constants
|
|
def v2i64_get_imm: SDNodeXForm<build_vector, [{
|
|
return SPU::get_v2i64_imm(N, *CurDAG);
|
|
}]>;
|
|
|
|
def v2i64Imm: PatLeaf<(build_vector), [{
|
|
return SPU::get_v2i64_imm(N, *CurDAG).getNode() != 0;
|
|
}], v2i64_get_imm>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Operand Definitions.
|
|
|
|
def s7imm: Operand<i8> {
|
|
let PrintMethod = "printS7ImmOperand";
|
|
}
|
|
|
|
def s7imm_i8: Operand<i8> {
|
|
let PrintMethod = "printS7ImmOperand";
|
|
}
|
|
|
|
def u7imm: Operand<i16> {
|
|
let PrintMethod = "printU7ImmOperand";
|
|
}
|
|
|
|
def u7imm_i8: Operand<i8> {
|
|
let PrintMethod = "printU7ImmOperand";
|
|
}
|
|
|
|
def u7imm_i32: Operand<i32> {
|
|
let PrintMethod = "printU7ImmOperand";
|
|
}
|
|
|
|
// Halfword, signed 10-bit constant
|
|
def s10imm : Operand<i16> {
|
|
let PrintMethod = "printS10ImmOperand";
|
|
}
|
|
|
|
def s10imm_i8: Operand<i8> {
|
|
let PrintMethod = "printS10ImmOperand";
|
|
}
|
|
|
|
def s10imm_i32: Operand<i32> {
|
|
let PrintMethod = "printS10ImmOperand";
|
|
}
|
|
|
|
def s10imm_i64: Operand<i64> {
|
|
let PrintMethod = "printS10ImmOperand";
|
|
}
|
|
|
|
// Unsigned 10-bit integers:
|
|
def u10imm: Operand<i16> {
|
|
let PrintMethod = "printU10ImmOperand";
|
|
}
|
|
|
|
def u10imm_i8: Operand<i8> {
|
|
let PrintMethod = "printU10ImmOperand";
|
|
}
|
|
|
|
def u10imm_i32: Operand<i32> {
|
|
let PrintMethod = "printU10ImmOperand";
|
|
}
|
|
|
|
def s16imm : Operand<i16> {
|
|
let PrintMethod = "printS16ImmOperand";
|
|
}
|
|
|
|
def s16imm_i8: Operand<i8> {
|
|
let PrintMethod = "printS16ImmOperand";
|
|
}
|
|
|
|
def s16imm_i32: Operand<i32> {
|
|
let PrintMethod = "printS16ImmOperand";
|
|
}
|
|
|
|
def s16imm_i64: Operand<i64> {
|
|
let PrintMethod = "printS16ImmOperand";
|
|
}
|
|
|
|
def s16imm_f32: Operand<f32> {
|
|
let PrintMethod = "printS16ImmOperand";
|
|
}
|
|
|
|
def s16imm_f64: Operand<f64> {
|
|
let PrintMethod = "printS16ImmOperand";
|
|
}
|
|
|
|
def u16imm_i64 : Operand<i64> {
|
|
let PrintMethod = "printU16ImmOperand";
|
|
}
|
|
|
|
def u16imm_i32 : Operand<i32> {
|
|
let PrintMethod = "printU16ImmOperand";
|
|
}
|
|
|
|
def u16imm : Operand<i16> {
|
|
let PrintMethod = "printU16ImmOperand";
|
|
}
|
|
|
|
def f16imm : Operand<f32> {
|
|
let PrintMethod = "printU16ImmOperand";
|
|
}
|
|
|
|
def s18imm : Operand<i32> {
|
|
let PrintMethod = "printS18ImmOperand";
|
|
}
|
|
|
|
def u18imm : Operand<i32> {
|
|
let PrintMethod = "printU18ImmOperand";
|
|
}
|
|
|
|
def u18imm_i64 : Operand<i64> {
|
|
let PrintMethod = "printU18ImmOperand";
|
|
}
|
|
|
|
def f18imm : Operand<f32> {
|
|
let PrintMethod = "printU18ImmOperand";
|
|
}
|
|
|
|
def f18imm_f64 : Operand<f64> {
|
|
let PrintMethod = "printU18ImmOperand";
|
|
}
|
|
|
|
// Negated 7-bit halfword rotate immediate operands
|
|
def rothNeg7imm : Operand<i32> {
|
|
let PrintMethod = "printROTHNeg7Imm";
|
|
}
|
|
|
|
def rothNeg7imm_i16 : Operand<i16> {
|
|
let PrintMethod = "printROTHNeg7Imm";
|
|
}
|
|
|
|
// Negated 7-bit word rotate immediate operands
|
|
def rotNeg7imm : Operand<i32> {
|
|
let PrintMethod = "printROTNeg7Imm";
|
|
}
|
|
|
|
def rotNeg7imm_i16 : Operand<i16> {
|
|
let PrintMethod = "printROTNeg7Imm";
|
|
}
|
|
|
|
def rotNeg7imm_i8 : Operand<i8> {
|
|
let PrintMethod = "printROTNeg7Imm";
|
|
}
|
|
|
|
def target : Operand<OtherVT> {
|
|
let PrintMethod = "printBranchOperand";
|
|
}
|
|
|
|
// Absolute address call target
|
|
def calltarget : Operand<iPTR> {
|
|
let PrintMethod = "printCallOperand";
|
|
let MIOperandInfo = (ops u18imm:$calldest);
|
|
}
|
|
|
|
// PC relative call target
|
|
def relcalltarget : Operand<iPTR> {
|
|
let PrintMethod = "printPCRelativeOperand";
|
|
let MIOperandInfo = (ops s16imm:$calldest);
|
|
}
|
|
|
|
// Branch targets:
|
|
def brtarget : Operand<OtherVT> {
|
|
let PrintMethod = "printPCRelativeOperand";
|
|
}
|
|
|
|
// Hint for branch target
|
|
def hbrtarget : Operand<OtherVT> {
|
|
let PrintMethod = "printHBROperand";
|
|
}
|
|
|
|
// Indirect call target
|
|
def indcalltarget : Operand<iPTR> {
|
|
let PrintMethod = "printCallOperand";
|
|
let MIOperandInfo = (ops ptr_rc:$calldest);
|
|
}
|
|
|
|
def symbolHi: Operand<i32> {
|
|
let PrintMethod = "printSymbolHi";
|
|
}
|
|
|
|
def symbolLo: Operand<i32> {
|
|
let PrintMethod = "printSymbolLo";
|
|
}
|
|
|
|
def symbolLSA: Operand<i32> {
|
|
let PrintMethod = "printSymbolLSA";
|
|
}
|
|
|
|
// Shuffle address memory operaand [s7imm(reg) d-format]
|
|
def shufaddr : Operand<iPTR> {
|
|
let PrintMethod = "printShufAddr";
|
|
let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
|
|
}
|
|
|
|
// memory s10imm(reg) operand
|
|
def dformaddr : Operand<iPTR> {
|
|
let PrintMethod = "printDFormAddr";
|
|
let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
|
|
}
|
|
|
|
// 256K local store address
|
|
// N.B.: The tblgen code generator expects to have two operands, an offset
|
|
// and a pointer. Of these, only the immediate is actually used.
|
|
def addr256k : Operand<iPTR> {
|
|
let PrintMethod = "printAddr256K";
|
|
let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg);
|
|
}
|
|
|
|
// memory s18imm(reg) operand
|
|
def memri18 : Operand<iPTR> {
|
|
let PrintMethod = "printMemRegImmS18";
|
|
let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg);
|
|
}
|
|
|
|
// memory register + register operand
|
|
def memrr : Operand<iPTR> {
|
|
let PrintMethod = "printMemRegReg";
|
|
let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b);
|
|
}
|
|
|
|
// Define SPU-specific addressing modes: These come in three basic
|
|
// flavors:
|
|
//
|
|
// D-form : [r+I10] (10-bit signed offset + reg)
|
|
// X-form : [r+r] (reg+reg)
|
|
// A-form : abs (256K LSA offset)
|
|
// D-form(2): [r+I7] (7-bit signed offset + reg)
|
|
|
|
def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr",
|
|
[], [SDNPWantRoot]>;
|
|
def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr",
|
|
[], [SDNPWantRoot]>;
|
|
def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr",
|
|
[], [SDNPWantRoot]>;
|
|
def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr",
|
|
[], [SDNPWantRoot]>;
|