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https://github.com/c64scene-ar/llvm-6502.git
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9fe2009956
TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.9 KiB
LLVM
54 lines
1.9 KiB
LLVM
; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=THUMB
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; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=ARM
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; rdar://7353541
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; rdar://7354376
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; The generated code is no where near ideal. It's not recognizing the two
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; constantpool entries being loaded can be merged into one.
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@GV = external global i32 ; <i32*> [#uses=2]
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define void @t(i32* nocapture %vals, i32 %c) nounwind {
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entry:
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; ARM: t:
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; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
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; ARM-NOT: ldr r{{[0-9]+}}, LCPI0_1
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; ARM: LPC0_0:
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; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
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; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
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; THUMB: t:
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%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb.nph
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bb.nph: ; preds = %entry
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; ARM: LCPI0_0:
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; ARM-NOT: LCPI0_1:
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; ARM: .section
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; THUMB: BB#1
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; THUMB: ldr.n r2, LCPI0_0
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; THUMB: add r2, pc
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; THUMB: ldr r{{[0-9]+}}, [r2]
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; THUMB: LBB0_2
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; THUMB: LCPI0_0:
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; THUMB-NOT: LCPI0_1:
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; THUMB: .section
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%.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %bb.nph
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%1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
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%i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
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%scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
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%2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
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%3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
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store i32 %3, i32* @GV, align 4
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%4 = add i32 %i.03, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
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br i1 %exitcond, label %return, label %bb
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return: ; preds = %bb, %entry
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ret void
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}
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