Evan Cheng 5de728cfe1 Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. ... This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-27 23:22:03 +00:00
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3DNow.s	Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.	2011-07-27 23:22:03 +00:00
dg.exp
padlock.s	Recognize the xstorerng alias for VIA PadLock's xstore instruction.	2011-06-30 01:38:03 +00:00
x86_64-avx-clmul-encoding.s
x86_64-avx-encoding.s	Revert r133452: "Emit movq for 64-bit register to XMM register moves..."	2011-06-21 17:35:13 +00:00
x86_64-encoding.s
x86_64-fma3-encoding.s
x86_64-imm-widths.s
x86_directives.s
x86_errors.s	Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.	2011-07-27 23:22:03 +00:00
x86_operands.s
x86-32-avx.s	Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.	2011-07-27 23:01:50 +00:00
x86-32-coverage.s	Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.	2011-07-27 23:22:03 +00:00
x86-32-fma3.s
x86-32.s
x86-64.s	Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a	2011-07-06 17:23:46 +00:00