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We would emit a libcall for a 64-bit atomic on x86 after SVN r212119. This was due to the misuse of hasCmpxchg16 to indicate if cmpxchg8b was supported on a 32-bit target. They were added at different times and would result in the border condition being mishandled. This fixes the border case to emit the cmpxchg8b instruction for 64-bit atomic operations on x86 at the cost of restoring a long-standing bug in the codegen. We emit a cmpxchg8b on all x86 targets even where the CPU does not support this instruction (pre-Pentium CPUs). Although this bug should be fixed, this was present prior to SVN r212119 and this change, so this is not really introducing a regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212956 91177308-0d34-0410-b5e6-96231b3b80d8
284 lines
9.7 KiB
C++
284 lines
9.7 KiB
C++
//===-- X86AtomicExpandPass.cpp - Expand illegal atomic instructions --0---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass (at IR level) to replace atomic instructions which
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// cannot be implemented as a single instruction with cmpxchg-based loops.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86TargetMachine.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-atomic-expand"
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namespace {
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class X86AtomicExpandPass : public FunctionPass {
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const X86TargetMachine *TM;
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public:
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static char ID; // Pass identification, replacement for typeid
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explicit X86AtomicExpandPass(const X86TargetMachine *TM)
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: FunctionPass(ID), TM(TM) {}
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bool runOnFunction(Function &F) override;
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bool expandAtomicInsts(Function &F);
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bool needsCmpXchgNb(Type *MemType);
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/// There are four kinds of atomic operations. Two never need expanding:
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/// cmpxchg is what we expand the others *to*, and loads are easily handled
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/// by ISelLowering. Atomicrmw and store can need expanding in some
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/// circumstances.
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bool shouldExpand(Instruction *Inst);
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/// 128-bit atomic stores (64-bit on i686) need to be implemented in terms
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/// of trivial cmpxchg16b loops. A simple store isn't necessarily atomic.
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bool shouldExpandStore(StoreInst *SI);
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/// Only some atomicrmw instructions need expanding -- some operations
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/// (e.g. max) have absolutely no architectural support; some (e.g. or) have
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/// limited support but can't return the previous value; some (e.g. add)
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/// have complete support in the instruction set.
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///
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/// Also, naturally, 128-bit operations always need to be expanded.
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bool shouldExpandAtomicRMW(AtomicRMWInst *AI);
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bool expandAtomicRMW(AtomicRMWInst *AI);
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bool expandAtomicStore(StoreInst *SI);
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};
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}
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char X86AtomicExpandPass::ID = 0;
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FunctionPass *llvm::createX86AtomicExpandPass(const X86TargetMachine *TM) {
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return new X86AtomicExpandPass(TM);
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}
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bool X86AtomicExpandPass::runOnFunction(Function &F) {
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SmallVector<Instruction *, 1> AtomicInsts;
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// Changing control-flow while iterating through it is a bad idea, so gather a
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// list of all atomic instructions before we start.
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for (BasicBlock &BB : F)
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for (Instruction &Inst : BB) {
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if (isa<AtomicRMWInst>(&Inst) ||
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(isa<StoreInst>(&Inst) && cast<StoreInst>(&Inst)->isAtomic()))
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AtomicInsts.push_back(&Inst);
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}
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bool MadeChange = false;
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for (Instruction *Inst : AtomicInsts) {
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if (!shouldExpand(Inst))
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continue;
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if (AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(Inst))
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MadeChange |= expandAtomicRMW(AI);
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if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
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MadeChange |= expandAtomicStore(SI);
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assert(MadeChange && "Atomic inst not expanded when it should be?");
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Inst->eraseFromParent();
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}
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return MadeChange;
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}
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/// Returns true if the operand type is 1 step up from the native width, and
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/// the corresponding cmpxchg8b or cmpxchg16b instruction is available
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/// (otherwise we leave them alone to become __sync_fetch_and_... calls).
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bool X86AtomicExpandPass::needsCmpXchgNb(llvm::Type *MemType) {
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const X86Subtarget &Subtarget = TM->getSubtarget<X86Subtarget>();
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unsigned OpWidth = MemType->getPrimitiveSizeInBits();
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if (OpWidth == 64)
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return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
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if (OpWidth == 128)
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return Subtarget.hasCmpxchg16b();
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return false;
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}
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bool X86AtomicExpandPass::shouldExpandAtomicRMW(AtomicRMWInst *AI) {
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const X86Subtarget &Subtarget = TM->getSubtarget<X86Subtarget>();
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unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
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if (needsCmpXchgNb(AI->getType()))
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return true;
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if (AI->getType()->getPrimitiveSizeInBits() > NativeWidth)
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return false;
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AtomicRMWInst::BinOp Op = AI->getOperation();
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switch (Op) {
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default:
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llvm_unreachable("Unknown atomic operation");
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case AtomicRMWInst::Xchg:
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case AtomicRMWInst::Add:
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case AtomicRMWInst::Sub:
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// It's better to use xadd, xsub or xchg for these in all cases.
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return false;
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case AtomicRMWInst::Or:
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case AtomicRMWInst::And:
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case AtomicRMWInst::Xor:
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// If the atomicrmw's result isn't actually used, we can just add a "lock"
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// prefix to a normal instruction for these operations.
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return !AI->use_empty();
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case AtomicRMWInst::Nand:
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case AtomicRMWInst::Max:
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case AtomicRMWInst::Min:
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case AtomicRMWInst::UMax:
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case AtomicRMWInst::UMin:
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// These always require a non-trivial set of data operations on x86. We must
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// use a cmpxchg loop.
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return true;
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}
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}
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bool X86AtomicExpandPass::shouldExpandStore(StoreInst *SI) {
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if (needsCmpXchgNb(SI->getValueOperand()->getType()))
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return true;
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return false;
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}
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bool X86AtomicExpandPass::shouldExpand(Instruction *Inst) {
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if (AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(Inst))
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return shouldExpandAtomicRMW(AI);
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if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
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return shouldExpandStore(SI);
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return false;
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}
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/// Emit IR to implement the given atomicrmw operation on values in registers,
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/// returning the new value.
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static Value *performAtomicOp(AtomicRMWInst::BinOp Op, IRBuilder<> &Builder,
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Value *Loaded, Value *Inc) {
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Value *NewVal;
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switch (Op) {
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case AtomicRMWInst::Xchg:
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return Inc;
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case AtomicRMWInst::Add:
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return Builder.CreateAdd(Loaded, Inc, "new");
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case AtomicRMWInst::Sub:
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return Builder.CreateSub(Loaded, Inc, "new");
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case AtomicRMWInst::And:
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return Builder.CreateAnd(Loaded, Inc, "new");
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case AtomicRMWInst::Nand:
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return Builder.CreateNot(Builder.CreateAnd(Loaded, Inc), "new");
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case AtomicRMWInst::Or:
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return Builder.CreateOr(Loaded, Inc, "new");
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case AtomicRMWInst::Xor:
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return Builder.CreateXor(Loaded, Inc, "new");
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case AtomicRMWInst::Max:
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NewVal = Builder.CreateICmpSGT(Loaded, Inc);
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return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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case AtomicRMWInst::Min:
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NewVal = Builder.CreateICmpSLE(Loaded, Inc);
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return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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case AtomicRMWInst::UMax:
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NewVal = Builder.CreateICmpUGT(Loaded, Inc);
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return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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case AtomicRMWInst::UMin:
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NewVal = Builder.CreateICmpULE(Loaded, Inc);
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return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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default:
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break;
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}
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llvm_unreachable("Unknown atomic op");
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}
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bool X86AtomicExpandPass::expandAtomicRMW(AtomicRMWInst *AI) {
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AtomicOrdering Order =
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AI->getOrdering() == Unordered ? Monotonic : AI->getOrdering();
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Value *Addr = AI->getPointerOperand();
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BasicBlock *BB = AI->getParent();
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Function *F = BB->getParent();
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LLVMContext &Ctx = F->getContext();
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// Given: atomicrmw some_op iN* %addr, iN %incr ordering
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//
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// The standard expansion we produce is:
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// [...]
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// %init_loaded = load atomic iN* %addr
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// br label %loop
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// loop:
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// %loaded = phi iN [ %init_loaded, %entry ], [ %new_loaded, %loop ]
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// %new = some_op iN %loaded, %incr
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// %pair = cmpxchg iN* %addr, iN %loaded, iN %new
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// %new_loaded = extractvalue { iN, i1 } %pair, 0
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// %success = extractvalue { iN, i1 } %pair, 1
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// br i1 %success, label %atomicrmw.end, label %loop
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// atomicrmw.end:
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// [...]
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BasicBlock *ExitBB = BB->splitBasicBlock(AI, "atomicrmw.end");
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BasicBlock *LoopBB = BasicBlock::Create(Ctx, "atomicrmw.start", F, ExitBB);
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// This grabs the DebugLoc from AI.
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IRBuilder<> Builder(AI);
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// The split call above "helpfully" added a branch at the end of BB (to the
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// wrong place), but we want a load. It's easiest to just remove
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// the branch entirely.
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std::prev(BB->end())->eraseFromParent();
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Builder.SetInsertPoint(BB);
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LoadInst *InitLoaded = Builder.CreateLoad(Addr);
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InitLoaded->setAlignment(AI->getType()->getPrimitiveSizeInBits());
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Builder.CreateBr(LoopBB);
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// Start the main loop block now that we've taken care of the preliminaries.
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Builder.SetInsertPoint(LoopBB);
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PHINode *Loaded = Builder.CreatePHI(AI->getType(), 2, "loaded");
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Loaded->addIncoming(InitLoaded, BB);
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Value *NewVal =
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performAtomicOp(AI->getOperation(), Builder, Loaded, AI->getValOperand());
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Value *Pair = Builder.CreateAtomicCmpXchg(
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Addr, Loaded, NewVal, Order,
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AtomicCmpXchgInst::getStrongestFailureOrdering(Order));
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Value *NewLoaded = Builder.CreateExtractValue(Pair, 0, "newloaded");
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Loaded->addIncoming(NewLoaded, LoopBB);
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Value *Success = Builder.CreateExtractValue(Pair, 1, "success");
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Builder.CreateCondBr(Success, ExitBB, LoopBB);
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AI->replaceAllUsesWith(NewLoaded);
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return true;
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}
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bool X86AtomicExpandPass::expandAtomicStore(StoreInst *SI) {
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// An atomic store might need cmpxchg16b (or 8b on x86) to execute. Express
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// this in terms of the usual expansion to "atomicrmw xchg".
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IRBuilder<> Builder(SI);
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AtomicOrdering Order =
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SI->getOrdering() == Unordered ? Monotonic : SI->getOrdering();
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AtomicRMWInst *AI =
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Builder.CreateAtomicRMW(AtomicRMWInst::Xchg, SI->getPointerOperand(),
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SI->getValueOperand(), Order);
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// Now we have an appropriate swap instruction, lower it as usual.
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if (shouldExpandAtomicRMW(AI)) {
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expandAtomicRMW(AI);
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AI->eraseFromParent();
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return true;
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}
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return AI;
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}
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