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760a46522a
The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216172 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
836 B
LLVM
25 lines
836 B
LLVM
; RUN: llc -mtriple=thumbv7m-apple-darwin -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-M3
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; RUN: llc -mtriple=thumbv7em-apple-darwin -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4
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; RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-M3
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; RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4
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define float @float_op(float %lhs, float %rhs) {
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%sum = fadd float %lhs, %rhs
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ret float %sum
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; CHECK-M3-LABEL: float_op:
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; CHECK-M3: bl ___addsf3
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; CHECK-M4-LABEL: float_op:
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; CHECK-M4: vadd.f32
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}
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define double @double_op(double %lhs, double %rhs) {
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%sum = fadd double %lhs, %rhs
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ret double %sum
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; CHECK-M3-LABEL: double_op:
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; CHECK-M3: bl ___adddf3
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; CHECK-M4-LABEL: double_op:
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; CHECK-M4: {{(blx|b.w)}} ___adddf3
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}
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