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have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
2009-05-10-CyclicDAG.ll | ||
2009-05-17-Rot.ll | ||
2009-05-17-Shift.ll | ||
2009-05-19-DoubleSplit.ll | ||
2009-08-25-DynamicStackAlloc.ll | ||
2009-09-18-AbsoluteAddr.ll | ||
2009-10-10-OrImpDef.ll | ||
2009-11-05-8BitLibcalls.ll | ||
2009-11-08-InvalidResNo.ll | ||
2009-11-20-NewNode.ll | ||
2009-12-21-FrameAddr.ll | ||
2009-12-22-InlineAsm.ll | ||
2010-04-07-DbgValueOtherTargets.ll | ||
2010-05-01-CombinerAnd.ll | ||
AddrMode-bis-rx.ll | ||
AddrMode-bis-xr.ll | ||
AddrMode-mov-rx.ll | ||
AddrMode-mov-xr.ll | ||
bit.ll | ||
dg.exp | ||
indirectbr2.ll | ||
indirectbr.ll | ||
inline-asm.ll | ||
Inst8mi.ll | ||
Inst8mm.ll | ||
Inst8mr.ll | ||
Inst8ri.ll | ||
Inst8rm.ll | ||
Inst8rr.ll | ||
Inst16mi.ll | ||
Inst16mm.ll | ||
Inst16mr.ll | ||
Inst16ri.ll | ||
Inst16rm.ll | ||
Inst16rr.ll | ||
mult-alt-generic-msp430.ll | ||
postinc.ll | ||
setcc.ll | ||
shifts.ll |