Evan Cheng 089751535d Avoiding overly aggressive latency scheduling. If the two nodes share an ... operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8		2010-10-29 18:09:28 +00:00
..
Alpha
ARM	Teach the DAG combiner to fold a splat of a splat. Radar 8597790.	2010-10-28 17:06:14 +00:00
Blackfin
CBackend
CellSPU	Change v64 datalayout in SPU.	2010-10-26 10:45:47 +00:00
CPP
Generic
MBlaze	Recommit 116986 with capitalization typo fixed.	2010-10-21 03:57:26 +00:00
Mips
MSP430
PowerPC	PowerPC varargs functions store live-in registers on the stack. Make sure we use	2010-10-11 20:43:09 +00:00
PTX	Add test case mov.ll for PTX device function	2010-10-19 13:21:51 +00:00
SPARC
SystemZ
Thumb
Thumb2	Avoiding overly aggressive latency scheduling. If the two nodes share an	2010-10-29 18:09:28 +00:00
X86	Fix pastos in handling of AVX cvttsd2si, PR8491.	2010-10-28 00:35:54 +00:00
XCore
thumb2-mul.ll