mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-03 02:30:00 +00:00
922d314e8f
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
313 lines
15 KiB
TableGen
313 lines
15 KiB
TableGen
//===- X86InstrControl.td - Control Flow Instructions ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 jump, return, call, and related instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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//
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// Return instructions.
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let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, FPForm = SpecialFP in {
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def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret",
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[(X86retflag 0)], IIC_RET>;
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def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"ret\t$amt",
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[(X86retflag timm:$amt)], IIC_RET_IMM>;
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def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"retw\t$amt",
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[], IIC_RET_IMM>, OpSize;
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def LRETL : I <0xCB, RawFrm, (outs), (ins),
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"lretl", [], IIC_RET>;
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def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
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"lretq", [], IIC_RET>;
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def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"lret\t$amt", [], IIC_RET>;
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def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"lretw\t$amt", [], IIC_RET>, OpSize;
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}
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// Unconditional branches.
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let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
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def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
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"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
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def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
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"jmp\t$dst", [], IIC_JMP_REL>;
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// FIXME : Intel syntax for JMP64pcrel32 such that it is not ambiguious
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// with JMP_1.
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def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
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"jmpq\t$dst", [], IIC_JMP_REL>;
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}
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// Conditional Branches.
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let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
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multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
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def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
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IIC_Jcc>;
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def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
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[(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB;
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}
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}
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defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
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defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
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defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
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defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
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defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
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defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
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defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
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defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
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defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
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defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
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defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
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defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
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defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
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defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
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defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
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defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
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// jcx/jecx/jrcx instructions.
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let isAsmParserOnly = 1, isBranch = 1, isTerminator = 1 in {
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// These are the 32-bit versions of this instruction for the asmparser. In
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// 32-bit mode, the address size prefix is jcxz and the unprefixed version is
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// jecxz.
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let Uses = [CX] in
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def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In32BitMode]>;
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let Uses = [ECX] in
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def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jecxz\t$dst", [], IIC_JCXZ>, Requires<[In32BitMode]>;
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// J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
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// In 64-bit mode, the address size prefix is jecxz and the unprefixed version
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// is jrcxz.
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let Uses = [ECX] in
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def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>;
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let Uses = [RCX] in
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def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>;
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}
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
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[(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>;
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def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
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[(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, Requires<[In32BitMode]>;
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def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
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[(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>;
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def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
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[(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, Requires<[In64BitMode]>;
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def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"ljmp{w}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>, OpSize;
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def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"ljmp{l}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>;
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def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
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"ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
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def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
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"ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize;
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def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
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"ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
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}
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// Loop instructions
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def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
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def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
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def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. ESP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [ESP] in {
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def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i32imm_pcrel:$dst,variable_ops),
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"call{l}\t$dst", [], IIC_CALL_RI>, Requires<[In32BitMode]>;
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def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
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"call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
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Requires<[In32BitMode]>;
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def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
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"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], IIC_CALL_MEM>,
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Requires<[In32BitMode]>;
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def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"lcall{w}\t{$seg, $off|$off, $seg}", [],
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IIC_CALL_FAR_PTR>, OpSize;
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def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"lcall{l}\t{$seg, $off|$off, $seg}", [],
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IIC_CALL_FAR_PTR>;
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def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
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"lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize;
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def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
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"lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
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// callw for 16 bit code for the assembler.
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let isAsmParserOnly = 1 in
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def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
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(outs), (ins i16imm_pcrel:$dst, variable_ops),
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"callw\t$dst", []>, OpSize;
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}
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// Tail call stuff.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1 in
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [ESP] in {
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def TCRETURNdi : PseudoI<(outs),
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(ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops), []>;
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def TCRETURNri : PseudoI<(outs),
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(ins GR32_TC:$dst, i32imm:$offset, variable_ops), []>;
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let mayLoad = 1 in
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def TCRETURNmi : PseudoI<(outs),
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(ins i32mem_TC:$dst, i32imm:$offset, variable_ops), []>;
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// FIXME: The should be pseudo instructions that are lowered when going to
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// mcinst.
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def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
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(ins i32imm_pcrel:$dst, variable_ops),
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"jmp\t$dst # TAILCALL",
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[], IIC_JMP_REL>;
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def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
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"", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
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let mayLoad = 1 in
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def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
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"jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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Uses = [RSP] in {
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// NOTE: this pattern doesn't match "X86call imm", because we do not know
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// that the offset between an arbitrary immediate and the call will fit in
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// the 32-bit pcrel field that we have.
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def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst, variable_ops),
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"call{q}\t$dst", [], IIC_CALL_RI>,
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Requires<[In64BitMode, NotWin64]>;
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def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
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"call{q}\t{*}$dst", [(X86call GR64:$dst)],
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IIC_CALL_RI>,
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Requires<[In64BitMode, NotWin64]>;
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def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
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"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
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IIC_CALL_MEM>,
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Requires<[In64BitMode, NotWin64]>;
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def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
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"lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
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}
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// FIXME: We need to teach codegen about single list of call-clobbered
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// registers.
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let isCall = 1, isCodeGenOnly = 1 in
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// All calls clobber the non-callee saved registers. RSP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, YMM_HI_6_15, EFLAGS],
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Uses = [RSP] in {
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def WINCALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst, variable_ops),
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"call{q}\t$dst", [], IIC_CALL_RI>,
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Requires<[IsWin64]>;
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def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
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"call{q}\t{*}$dst",
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[(X86call GR64:$dst)], IIC_CALL_RI>,
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Requires<[IsWin64]>;
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def WINCALL64m : I<0xFF, MRM2m, (outs),
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(ins i64mem:$dst,variable_ops),
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"call{q}\t{*}$dst",
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[(X86call (loadi64 addr:$dst))], IIC_CALL_MEM>,
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Requires<[IsWin64]>;
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}
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let isCall = 1, isCodeGenOnly = 1 in
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// __chkstk(MSVC): clobber R10, R11 and EFLAGS.
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// ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
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let Defs = [RAX, R10, R11, RSP, EFLAGS],
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Uses = [RSP] in {
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def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst, variable_ops),
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"call{q}\t$dst", [], IIC_CALL_RI>,
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Requires<[IsWin64]>;
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}
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1 in
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// AMD64 cc clobbers RSI, RDI, XMM6-XMM15.
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let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
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FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
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MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
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Uses = [RSP],
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usesCustomInserter = 1 in {
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def TCRETURNdi64 : PseudoI<(outs),
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(ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
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[]>;
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def TCRETURNri64 : PseudoI<(outs),
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(ins ptr_rc_tailcall:$dst, i32imm:$offset, variable_ops), []>;
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let mayLoad = 1 in
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def TCRETURNmi64 : PseudoI<(outs),
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(ins i64mem_TC:$dst, i32imm:$offset, variable_ops), []>;
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def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
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(ins i64i32imm_pcrel:$dst, variable_ops),
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"jmp\t$dst # TAILCALL", [], IIC_JMP_REL>;
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def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst, variable_ops),
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"jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
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let mayLoad = 1 in
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def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
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"jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
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}
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