mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
497204a94b
re-materialization of immediate loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167153 91177308-0d34-0410-b5e6-96231b3b80d8
349 lines
16 KiB
TableGen
349 lines
16 KiB
TableGen
//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64 instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def shamt_64 : Operand<i64>;
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// Unsigned Operand
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def uimm16_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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// Transformation Function - get Imm - 32.
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def Subtract32 : SDNodeXForm<imm, [{
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return getImm(N, (unsigned)N->getZExtValue() - 32);
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}]>;
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// shamt must fit in 6 bits.
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def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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// Shifts
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// 64-bit shift instructions.
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let DecoderNamespace = "Mips64" in {
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class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
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SDNode OpNode>:
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shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt6, shamt,
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CPU64Regs>;
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// Mul, Div
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class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
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Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
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class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
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Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
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multiclass Atomic2Ops64<PatFrag Op, string Opstr> {
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def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>,
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Requires<[NotN64, HasStandardEncoding]>;
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def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>,
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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}
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multiclass AtomicCmpSwap64<PatFrag Op, string Width> {
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def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>,
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Requires<[NotN64, HasStandardEncoding]>;
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def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>,
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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}
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}
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let usesCustomInserter = 1, Predicates = [HasMips64, HasStandardEncoding],
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DecoderNamespace = "Mips64" in {
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defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
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defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;
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defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">;
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defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">;
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defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">;
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defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">;
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defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">;
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defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">;
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}
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "Mips64" in {
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/// Arithmetic Instructions (ALU Immediate)
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def DADDi : ArithOverflowI<0x18, "daddi", add, simm16_64, immSExt16,
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CPU64Regs>;
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def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
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CPU64Regs>, IsAsCheapAsAMove;
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def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
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def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
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def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
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def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>;
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def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
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def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADD : ArithOverflowR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>;
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def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
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def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
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def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
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def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
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def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>;
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def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>;
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def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
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def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
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/// Shift Instructions
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def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
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def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
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def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
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def DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>;
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def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>;
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def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>;
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let Pattern = []<dag> in {
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def DSLL32 : shift_rotate_imm64<0x3c, 0x00, "dsll32", shl>;
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def DSRL32 : shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl>;
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def DSRA32 : shift_rotate_imm64<0x3f, 0x00, "dsra32", sra>;
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}
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}
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// Rotate Instructions
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let Predicates = [HasMips64r2, HasStandardEncoding],
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DecoderNamespace = "Mips64" in {
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def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
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def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
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}
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let DecoderNamespace = "Mips64" in {
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/// Load and Store Instructions
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/// aligned
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defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
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defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
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defm LH64 : LoadM64<0x21, "lh", sextloadi16>;
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defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>;
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defm LW64 : LoadM64<0x23, "lw", sextloadi32>;
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defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>;
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defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
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defm SH64 : StoreM64<0x29, "sh", truncstorei16>;
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defm SW64 : StoreM64<0x2b, "sw", truncstorei32>;
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defm LD : LoadM64<0x37, "ld", load>;
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defm SD : StoreM64<0x3f, "sd", store>;
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/// load/store left/right
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let isCodeGenOnly = 1 in {
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defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>;
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defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>;
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defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>;
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defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>;
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}
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defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>;
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defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>;
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defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>;
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defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>;
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/// Load-linked, Store-conditional
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def LLD : LLBase<0x34, "lld", CPU64Regs, mem>,
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Requires<[NotN64, HasStandardEncoding]>;
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def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>,
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>,
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Requires<[NotN64, HasStandardEncoding]>;
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def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>,
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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/// Jump and Branch Instructions
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def JR64 : IndirectBranch<CPU64Regs>;
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def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
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def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
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def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
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def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
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def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>;
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def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
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}
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let DecoderNamespace = "Mips64" in
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def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>;
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def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, IsTailCall;
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let DecoderNamespace = "Mips64" in {
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/// Multiply and Divide Instructions.
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def DMULT : Mult64<0x1c, "dmult", IIImul>;
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def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
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def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
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def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
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def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>;
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def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
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def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
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def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
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/// Sign Ext In Register Instructions.
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def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>;
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def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>;
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/// Count Leading
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def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
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def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
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/// Double Word Swap Bytes/HalfWords
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def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>;
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def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
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def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
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}
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let Uses = [SP_64], DecoderNamespace = "Mips64" in
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def DynAlloc64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
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Requires<[IsN64, HasStandardEncoding]>;
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let DecoderNamespace = "Mips64" in {
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def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
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def DEXT : ExtBase<3, "dext", CPU64Regs>;
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let Pattern = []<dag> in {
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def DEXTU : ExtBase<2, "dextu", CPU64Regs>;
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def DEXTM : ExtBase<1, "dextm", CPU64Regs>;
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}
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def DINS : InsBase<7, "dins", CPU64Regs>;
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let Pattern = []<dag> in {
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def DINSU : InsBase<6, "dinsu", CPU64Regs>;
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def DINSM : InsBase<5, "dinsm", CPU64Regs>;
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}
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let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
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def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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"dsll\t$rd, $rt, 32", [], IIAlu>;
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def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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"sll\t$rd, $rt, 0", [], IIAlu>;
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def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
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"sll\t$rd, $rt, 0", [], IIAlu>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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// extended loads
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let Predicates = [NotN64, HasStandardEncoding] in {
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
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def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
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def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
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}
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let Predicates = [IsN64, HasStandardEncoding] in {
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def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
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def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
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}
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// hi/lo relocs
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def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
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def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
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def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
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def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
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def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
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def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
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def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
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def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
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def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
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def : MipsPat<(MipsLo tglobaltlsaddr:$in),
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(DADDiu ZERO_64, tglobaltlsaddr:$in)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
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(DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
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(DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
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(DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
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def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
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(DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
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def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
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def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
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def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
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def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
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def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
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def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
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defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
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ZERO_64>;
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// setcc patterns
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defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
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defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
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// select MipsDynAlloc
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def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>,
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Requires<[IsN64, HasStandardEncoding]>;
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// truncate
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def : MipsPat<(i32 (trunc CPU64Regs:$src)),
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(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
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Requires<[IsN64, HasStandardEncoding]>;
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// 32-to-64-bit extension
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def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
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def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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// Sign extend in register
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def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
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(SLL64_64 CPU64Regs:$src)>;
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// bswap MipsPattern
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def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>;
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64" in {
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def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt),
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(ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
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def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel),
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(ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">;
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def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt),
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(ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
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def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel),
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(ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">;
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def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt),
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(ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">;
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def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel),
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(ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">;
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def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt),
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(ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">;
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def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel),
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(ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">;
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}
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// Two operand (implicit 0 selector) versions:
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def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
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def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
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