llvm-6502/test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt
Renato Golin 09e28e39f0 Thumb2 M-class MSR instruction support changes
This patch implements a few changes related to the Thumb2 M-class MSR instruction:
 * better handling of unpredictable encodings,
 * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP
   extension is available, preferred output of MSR APSR moves with the _<bits>
   suffix for v7-M.

Patch by Petr Pavlu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-01 11:25:07 +00:00

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# RUN: not llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck --check-prefix=CHECK %s
# RUN: not llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
#------------------------------------------------------------------------------
# Undefined encodings for mrs
#------------------------------------------------------------------------------
# invalid SYSm
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0xef 0xf3 0x80 0x80]
[0xef 0xf3 0x80 0x80]
#------------------------------------------------------------------------------
# Undefined encodings for msr
#------------------------------------------------------------------------------
# invalid mask = '00'
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: [0x80 0xf3 0x00 0x80]
[0x80 0xf3 0x00 0x80]
# invalid mask = '11' with SYSm not in {0..3}
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: [0x80 0xf3 0x05 0x8c]
[0x80 0xf3 0x05 0x8c]
# invalid mask = '01' (ThumbV7M does not have the DSP extension)
# CHECK-V7M: warning: potentially undefined instruction encoding
# CHECK-V7M-NEXT: [0x80 0xf3 0x00 0x84]
[0x80 0xf3 0x00 0x84]
# invalid SYSm
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x80 0xf3 0x80 0x88]
[0x80 0xf3 0x80 0x88]