llvm-6502/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt
Vladimir Sukharev c8a807c1c5 [ARM] Add v8.1a "Rounding Double Multiply Add/Subtract" extension
Reviewers: t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8503


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233301 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-26 18:29:02 +00:00

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# RUN: not llvm-mc -triple thumbv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s
# Check, if sizes 00 and 11 are undefined for RDMA
[0x01,0xff,0x12,0x0b] # vqrdmlah.s8 d0, d1, d2
[0x31,0xff,0x12,0x0b] # vqrdmlah.s64 d0, d1, d2
[0x02,0xff,0x54,0x0b] # vqrdmlah.s8 q0, q1, q2
[0x06,0xff,0x50,0x4b] # vqrdmlah.s64 q2, q3, q0
[0x01,0xff,0x12,0x0c] # vqrdmlsh.s8 d0, d1, d2
[0x31,0xff,0x12,0x0c] # vqrdmlsh.s64 d0, d1, d2
[0x02,0xff,0x54,0x0c] # vqrdmlsh.s8 q0, q1, q2
[0x32,0xff,0x54,0x0c] # vqrdmlsh.s64 q0, q1, q2
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x01,0xff,0x12,0x0b] # vqrdmlah.s8 d0, d1, d2
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x31,0xff,0x12,0x0b] # vqrdmlah.s64 d0, d1, d2
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x02,0xff,0x54,0x0b] # vqrdmlah.s8 q0, q1, q2
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x06,0xff,0x50,0x4b] # vqrdmlah.s64 q2, q3, q0
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x01,0xff,0x12,0x0c] # vqrdmlsh.s8 d0, d1, d2
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x31,0xff,0x12,0x0c] # vqrdmlsh.s64 d0, d1, d2
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x02,0xff,0x54,0x0c] # vqrdmlsh.s8 q0, q1, q2
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x32,0xff,0x54,0x0c] # vqrdmlsh.s64 q0, q1, q2
# CHECK-NEXT: ^
[0x81,0xef,0x42,0x0e] # vqrdmlah.s8 d0, d1, d2[0]
[0xb1,0xef,0x42,0x0e] # vqrdmlah.s64 d0, d1, d2[0]
[0x82,0xff,0x42,0x0e] # vqrdmlah.s8 q0, q1, d2[0]
[0xb2,0xff,0x42,0x0e] # vqrdmlah.s64 q0, q1, d2[0]
[0x81,0xef,0x42,0x0f] # vqrdmlsh.s8 d0, d1, d2[0]
[0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64 d0, d1, d2[0]
[0x82,0xff,0x42,0x0f] # vqrdmlsh.s8 q0, q1, d2[0]
[0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64 q0, q1, d2[0]
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x81,0xef,0x42,0x0e] # vqrdmlah.s8 d0, d1, d2[0]
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0xb1,0xef,0x42,0x0e] # vqrdmlah.s64 d0, d1, d2[0]
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x82,0xff,0x42,0x0e] # vqrdmlah.s8 q0, q1, d2[0]
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0xb2,0xff,0x42,0x0e] # vqrdmlah.s64 q0, q1, d2[0]
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x81,0xef,0x42,0x0f] # vqrdmlsh.s8 d0, d1, d2[0]
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64 d0, d1, d2[0]
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0x82,0xff,0x42,0x0f] # vqrdmlsh.s8 q0, q1, d2[0]
# CHECK-NEXT: ^
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64 q0, q1, d2[0]
# CHECK-NEXT: ^