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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
142 lines
5.0 KiB
C++
142 lines
5.0 KiB
C++
//===-- FPMover.cpp - Sparc double-precision floating point move fixer ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Expand FpMOVD/FpABSD/FpNEGD instructions into their single-precision pieces.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "fpmover"
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#include "Sparc.h"
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#include "SparcSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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STATISTIC(NumFpDs , "Number of instructions translated");
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STATISTIC(NoopFpDs, "Number of noop instructions removed");
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namespace {
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struct FPMover : public MachineFunctionPass {
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/// Target machine description which we query for reg. names, data
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/// layout, etc.
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///
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TargetMachine &TM;
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static char ID;
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explicit FPMover(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm) { }
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virtual const char *getPassName() const {
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return "Sparc Double-FP Move Fixer";
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}
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F);
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};
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char FPMover::ID = 0;
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} // end of anonymous namespace
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/// createSparcFPMoverPass - Returns a pass that turns FpMOVD
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/// instructions into FMOVS instructions
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///
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FunctionPass *llvm::createSparcFPMoverPass(TargetMachine &tm) {
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return new FPMover(tm);
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}
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/// getDoubleRegPair - Given a DFP register, return the even and odd FP
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/// registers that correspond to it.
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static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg,
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unsigned &OddReg) {
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static const uint16_t EvenHalvesOfPairs[] = {
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SP::F0, SP::F2, SP::F4, SP::F6, SP::F8, SP::F10, SP::F12, SP::F14,
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SP::F16, SP::F18, SP::F20, SP::F22, SP::F24, SP::F26, SP::F28, SP::F30
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};
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static const uint16_t OddHalvesOfPairs[] = {
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SP::F1, SP::F3, SP::F5, SP::F7, SP::F9, SP::F11, SP::F13, SP::F15,
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SP::F17, SP::F19, SP::F21, SP::F23, SP::F25, SP::F27, SP::F29, SP::F31
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};
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static const uint16_t DoubleRegsInOrder[] = {
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SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8,
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SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15
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};
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for (unsigned i = 0; i < array_lengthof(DoubleRegsInOrder); ++i)
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if (DoubleRegsInOrder[i] == DoubleReg) {
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EvenReg = EvenHalvesOfPairs[i];
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OddReg = OddHalvesOfPairs[i];
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return;
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}
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llvm_unreachable("Can't find reg");
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}
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/// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB.
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///
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bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
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MachineInstr *MI = I++;
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DebugLoc dl = MI->getDebugLoc();
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if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD ||
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MI->getOpcode() == SP::FpNEGD) {
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Changed = true;
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unsigned DestDReg = MI->getOperand(0).getReg();
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unsigned SrcDReg = MI->getOperand(1).getReg();
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if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) {
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MBB.erase(MI); // Eliminate the noop copy.
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++NoopFpDs;
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continue;
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}
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unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0;
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getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg);
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getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg);
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const TargetInstrInfo *TII = TM.getInstrInfo();
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if (MI->getOpcode() == SP::FpMOVD)
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MI->setDesc(TII->get(SP::FMOVS));
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else if (MI->getOpcode() == SP::FpNEGD)
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MI->setDesc(TII->get(SP::FNEGS));
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else if (MI->getOpcode() == SP::FpABSD)
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MI->setDesc(TII->get(SP::FABSS));
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else
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llvm_unreachable("Unknown opcode!");
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MI->getOperand(0).setReg(EvenDestReg);
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MI->getOperand(1).setReg(EvenSrcReg);
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DEBUG(errs() << "FPMover: the modified instr is: " << *MI);
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// Insert copy for the other half of the double.
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if (DestDReg != SrcDReg) {
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MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
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.addReg(OddSrcReg);
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DEBUG(errs() << "FPMover: the inserted instr is: " << *MI);
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}
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++NumFpDs;
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}
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}
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return Changed;
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}
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bool FPMover::runOnMachineFunction(MachineFunction &F) {
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// If the target has V9 instructions, the fp-mover pseudos will never be
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// emitted. Avoid a scan of the instructions to improve compile time.
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if (TM.getSubtarget<SparcSubtarget>().isV9())
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return false;
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bool Changed = false;
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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return Changed;
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}
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