mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-29 13:29:28 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183067 91177308-0d34-0410-b5e6-96231b3b80d8
208 lines
6.7 KiB
C++
208 lines
6.7 KiB
C++
//===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Sparc implementation of TargetFrameLowering class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "SparcFrameLowering.h"
|
|
#include "SparcInstrInfo.h"
|
|
#include "SparcMachineFunctionInfo.h"
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
#include "llvm/CodeGen/MachineModuleInfo.h"
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
#include "llvm/IR/DataLayout.h"
|
|
#include "llvm/IR/Function.h"
|
|
#include "llvm/Support/CommandLine.h"
|
|
#include "llvm/Target/TargetOptions.h"
|
|
|
|
using namespace llvm;
|
|
|
|
static cl::opt<bool>
|
|
DisableLeafProc("disable-sparc-leaf-proc",
|
|
cl::init(true),
|
|
cl::desc("Disable Sparc leaf procedure optimization."),
|
|
cl::Hidden);
|
|
|
|
|
|
void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
|
|
SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
|
|
|
|
MachineBasicBlock &MBB = MF.front();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const SparcInstrInfo &TII =
|
|
*static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
|
|
|
|
// Get the number of bytes to allocate from the FrameInfo
|
|
int NumBytes = (int) MFI->getStackSize();
|
|
|
|
unsigned SAVEri = SP::SAVEri;
|
|
unsigned SAVErr = SP::SAVErr;
|
|
if (FuncInfo->isLeafProc()) {
|
|
if (NumBytes == 0)
|
|
return;
|
|
SAVEri = SP::ADDri;
|
|
SAVErr = SP::ADDrr;
|
|
}
|
|
NumBytes = - SubTarget.getAdjustedFrameSize(NumBytes);
|
|
|
|
if (NumBytes >= -4096) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(SAVEri), SP::O6)
|
|
.addReg(SP::O6).addImm(NumBytes);
|
|
} else {
|
|
// Emit this the hard way. This clobbers G1 which we always know is
|
|
// available here.
|
|
unsigned OffHi = (unsigned)NumBytes >> 10U;
|
|
BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
|
|
// Emit G1 = G1 + I6
|
|
BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
|
|
.addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
|
|
BuildMI(MBB, MBBI, dl, TII.get(SAVErr), SP::O6)
|
|
.addReg(SP::O6).addReg(SP::G1);
|
|
}
|
|
}
|
|
|
|
void SparcFrameLowering::
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
if (!hasReservedCallFrame(MF)) {
|
|
MachineInstr &MI = *I;
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
int Size = MI.getOperand(0).getImm();
|
|
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
|
|
Size = -Size;
|
|
const SparcInstrInfo &TII =
|
|
*static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
|
|
if (Size)
|
|
BuildMI(MBB, I, DL, TII.get(SP::ADDri), SP::O6).addReg(SP::O6)
|
|
.addImm(Size);
|
|
}
|
|
MBB.erase(I);
|
|
}
|
|
|
|
|
|
void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
|
|
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
|
const SparcInstrInfo &TII =
|
|
*static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
|
|
DebugLoc dl = MBBI->getDebugLoc();
|
|
assert(MBBI->getOpcode() == SP::RETL &&
|
|
"Can only put epilog before 'retl' instruction!");
|
|
if (!FuncInfo->isLeafProc()) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
|
|
.addReg(SP::G0);
|
|
return;
|
|
}
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
int NumBytes = (int) MFI->getStackSize();
|
|
if (NumBytes == 0)
|
|
return;
|
|
|
|
NumBytes = SubTarget.getAdjustedFrameSize(NumBytes);
|
|
|
|
if (NumBytes < 4096) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
|
|
.addReg(SP::O6).addImm(NumBytes);
|
|
} else {
|
|
// Emit this the hard way. This clobbers G1 which we always know is
|
|
// available here.
|
|
unsigned OffHi = (unsigned)NumBytes >> 10U;
|
|
BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
|
|
// Emit G1 = G1 + I6
|
|
BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
|
|
.addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
|
|
BuildMI(MBB, MBBI, dl, TII.get(SP::ADDrr), SP::O6)
|
|
.addReg(SP::O6).addReg(SP::G1);
|
|
}
|
|
}
|
|
|
|
bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
|
|
//Reserve call frame if there are no variable sized objects on the stack
|
|
return !MF.getFrameInfo()->hasVarSizedObjects();
|
|
}
|
|
|
|
// hasFP - Return true if the specified function should have a dedicated frame
|
|
// pointer register. This is true if the function has variable sized allocas or
|
|
// if frame pointer elimination is disabled.
|
|
bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
return MF.getTarget().Options.DisableFramePointerElim(MF) ||
|
|
MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
|
|
}
|
|
|
|
|
|
static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
|
|
{
|
|
|
|
for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
|
|
if (MRI->isPhysRegUsed(reg))
|
|
return false;
|
|
|
|
for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
|
|
if (MRI->isPhysRegUsed(reg))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
|
|
{
|
|
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
return !(MFI->hasCalls() // has calls
|
|
|| MRI.isPhysRegUsed(SP::L0) // Too many registers needed
|
|
|| MRI.isPhysRegUsed(SP::O6) // %SP is used
|
|
|| hasFP(MF)); // need %FP
|
|
}
|
|
|
|
void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
|
|
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
//remap %i[0-7] to %o[0-7]
|
|
for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
|
|
if (!MRI.isPhysRegUsed(reg))
|
|
continue;
|
|
unsigned mapped_reg = (reg - SP::I0 + SP::O0);
|
|
assert(!MRI.isPhysRegUsed(mapped_reg));
|
|
|
|
//Replace I register with O register
|
|
MRI.replaceRegWith(reg, mapped_reg);
|
|
|
|
//mark the reg unused.
|
|
MRI.setPhysRegUnused(reg);
|
|
}
|
|
|
|
assert(verifyLeafProcRegUse(&MRI));
|
|
#ifdef XDEBUG
|
|
MF.verify(0, "After LeafProc Remapping");
|
|
#endif
|
|
}
|
|
|
|
void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
|
|
(MachineFunction &MF, RegScavenger *RS) const {
|
|
|
|
if (!DisableLeafProc && isLeafProc(MF)) {
|
|
SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
|
|
MFI->setLeafProc(true);
|
|
|
|
remapRegsForLeafProc(MF);
|
|
}
|
|
|
|
}
|