mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-25 14:30:32 +00:00
fcb25e60f5
We are going to use the same registers for 32-bit and 64-bit values, but in two different register classes. The I64Regs register class has a larger spill size and alignment. The addition of an i64 register class confuses TableGen's type inference, so it is necessary to clarify the type of some immediates and the G0 register. In 64-bit mode, pointers are i64 and should use the I64Regs register class. Implement getPointerRegClass() to dynamically provide the pointer register class depending on the subtarget. Use ptr_rc and iPTR for memory operands. Finally, add the i64 type to the IntRegs register class. This register class is not used to hold i64 values, I64Regs is for that. The type is required to appease TableGen's type checking in output patterns like this: def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and TableGen doesn't know to check the type of register sub-classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178522 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.8 KiB
C++
60 lines
1.8 KiB
C++
//===-- SparcRegisterInfo.h - Sparc Register Information Impl ---*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Sparc implementation of the TargetRegisterInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef SPARCREGISTERINFO_H
|
|
#define SPARCREGISTERINFO_H
|
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
|
|
|
#define GET_REGINFO_HEADER
|
|
#include "SparcGenRegisterInfo.inc"
|
|
|
|
namespace llvm {
|
|
|
|
class SparcSubtarget;
|
|
class TargetInstrInfo;
|
|
class Type;
|
|
|
|
struct SparcRegisterInfo : public SparcGenRegisterInfo {
|
|
SparcSubtarget &Subtarget;
|
|
const TargetInstrInfo &TII;
|
|
|
|
SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
|
|
|
|
/// Code Generation virtual methods...
|
|
const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
|
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const;
|
|
|
|
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
|
|
unsigned Kind) const;
|
|
|
|
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, unsigned FIOperandNum,
|
|
RegScavenger *RS = NULL) const;
|
|
|
|
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
|
|
RegScavenger *RS = NULL) const;
|
|
|
|
// Debug information queries.
|
|
unsigned getFrameRegister(const MachineFunction &MF) const;
|
|
|
|
// Exception handling queries.
|
|
unsigned getEHExceptionRegister() const;
|
|
unsigned getEHHandlerRegister() const;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|