mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33512 91177308-0d34-0410-b5e6-96231b3b80d8
623 lines
23 KiB
C++
623 lines
23 KiB
C++
//===-- ARMConstantIslandPass.cpp - ARM constant islands --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that splits the constant pool up into 'islands'
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// which are scattered through-out the function. This is required due to the
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// limited pc-relative displacements that ARM has.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-cp-islands"
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#include "ARM.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMInstrInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include <iostream>
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using namespace llvm;
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STATISTIC(NumSplit, "Number of uncond branches inserted");
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namespace {
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/// ARMConstantIslands - Due to limited pc-relative displacements, ARM
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/// requires constant pool entries to be scattered among the instructions
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/// inside a function. To do this, it completely ignores the normal LLVM
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/// constant pool, instead, it places constants where-ever it feels like with
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/// special instructions.
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///
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/// The terminology used in this pass includes:
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/// Islands - Clumps of constants placed in the function.
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/// Water - Potential places where an island could be formed.
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/// CPE - A constant pool entry that has been placed somewhere, which
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/// tracks a list of users.
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class VISIBILITY_HIDDEN ARMConstantIslands : public MachineFunctionPass {
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/// NextUID - Assign unique ID's to CPE's.
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unsigned NextUID;
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/// BBSizes - The size of each MachineBasicBlock in bytes of code, indexed
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/// by MBB Number.
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std::vector<unsigned> BBSizes;
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/// WaterList - A sorted list of basic blocks where islands could be placed
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/// (i.e. blocks that don't fall through to the following block, due
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/// to a return, unreachable, or unconditional branch).
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std::vector<MachineBasicBlock*> WaterList;
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/// CPUser - One user of a constant pool, keeping the machine instruction
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/// pointer, the constant pool being referenced, and the max displacement
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/// allowed from the instruction to the CP.
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struct CPUser {
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MachineInstr *MI;
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MachineInstr *CPEMI;
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unsigned MaxDisp;
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CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp)
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: MI(mi), CPEMI(cpemi), MaxDisp(maxdisp) {}
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};
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/// CPUsers - Keep track of all of the machine instructions that use various
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/// constant pools and their max displacement.
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std::vector<CPUser> CPUsers;
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/// ImmBranch - One per immediate branch, keeping the machine instruction
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/// pointer, conditional or unconditional, the max displacement,
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/// and (if isCond is true) the corresponding unconditional branch
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/// opcode.
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struct ImmBranch {
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MachineInstr *MI;
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unsigned MaxDisp : 31;
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bool isCond : 1;
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int UncondBr;
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ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, int ubr)
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: MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
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};
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/// Branches - Keep track of all the immediate branch instructions.
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///
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std::vector<ImmBranch> ImmBranches;
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const TargetInstrInfo *TII;
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const TargetAsmInfo *TAI;
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public:
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "ARM constant island placement and branch shortening pass";
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}
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private:
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void DoInitialPlacement(MachineFunction &Fn,
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std::vector<MachineInstr*> &CPEMIs);
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void InitialFunctionScan(MachineFunction &Fn,
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const std::vector<MachineInstr*> &CPEMIs);
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void SplitBlockBeforeInstr(MachineInstr *MI);
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void UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB);
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bool HandleConstantPoolUser(MachineFunction &Fn, CPUser &U);
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bool FixUpImmediateBranch(MachineFunction &Fn, ImmBranch &Br);
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unsigned GetInstSize(MachineInstr *MI) const;
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unsigned GetOffsetOf(MachineInstr *MI) const;
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unsigned GetOffsetOf(MachineBasicBlock *MBB) const;
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};
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}
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/// createARMConstantIslandPass - returns an instance of the constpool
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/// island pass.
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FunctionPass *llvm::createARMConstantIslandPass() {
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return new ARMConstantIslands();
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}
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bool ARMConstantIslands::runOnMachineFunction(MachineFunction &Fn) {
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// If there are no constants, there is nothing to do.
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MachineConstantPool &MCP = *Fn.getConstantPool();
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if (MCP.isEmpty()) return false;
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TII = Fn.getTarget().getInstrInfo();
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TAI = Fn.getTarget().getTargetAsmInfo();
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// Renumber all of the machine basic blocks in the function, guaranteeing that
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// the numbers agree with the position of the block in the function.
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Fn.RenumberBlocks();
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// Perform the initial placement of the constant pool entries. To start with,
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// we put them all at the end of the function.
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std::vector<MachineInstr*> CPEMIs;
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DoInitialPlacement(Fn, CPEMIs);
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/// The next UID to take is the first unused one.
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NextUID = CPEMIs.size();
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// Do the initial scan of the function, building up information about the
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// sizes of each block, the location of all the water, and finding all of the
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// constant pool users.
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InitialFunctionScan(Fn, CPEMIs);
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CPEMIs.clear();
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// Iteratively place constant pool entries until there is no change.
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bool MadeChange;
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do {
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MadeChange = false;
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for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
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MadeChange |= HandleConstantPoolUser(Fn, CPUsers[i]);
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for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
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MadeChange |= FixUpImmediateBranch(Fn, ImmBranches[i]);
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} while (MadeChange);
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BBSizes.clear();
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WaterList.clear();
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CPUsers.clear();
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ImmBranches.clear();
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return true;
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}
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/// DoInitialPlacement - Perform the initial placement of the constant pool
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/// entries. To start with, we put them all at the end of the function.
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void ARMConstantIslands::DoInitialPlacement(MachineFunction &Fn,
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std::vector<MachineInstr*> &CPEMIs){
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// Create the basic block to hold the CPE's.
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MachineBasicBlock *BB = new MachineBasicBlock();
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Fn.getBasicBlockList().push_back(BB);
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// Add all of the constants from the constant pool to the end block, use an
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// identity mapping of CPI's to CPE's.
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const std::vector<MachineConstantPoolEntry> &CPs =
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Fn.getConstantPool()->getConstants();
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const TargetData &TD = *Fn.getTarget().getTargetData();
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for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
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unsigned Size = TD.getTypeSize(CPs[i].getType());
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// Verify that all constant pool entries are a multiple of 4 bytes. If not,
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// we would have to pad them out or something so that instructions stay
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// aligned.
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assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!");
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MachineInstr *CPEMI =
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BuildMI(BB, TII->get(ARM::CONSTPOOL_ENTRY))
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.addImm(i).addConstantPoolIndex(i).addImm(Size);
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CPEMIs.push_back(CPEMI);
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DEBUG(std::cerr << "Moved CPI#" << i << " to end of function as #"
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<< i << "\n");
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}
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}
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/// BBHasFallthrough - Return true of the specified basic block can fallthrough
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/// into the block immediately after it.
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static bool BBHasFallthrough(MachineBasicBlock *MBB) {
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// Get the next machine basic block in the function.
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MachineFunction::iterator MBBI = MBB;
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if (next(MBBI) == MBB->getParent()->end()) // Can't fall off end of function.
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return false;
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MachineBasicBlock *NextBB = next(MBBI);
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for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
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E = MBB->succ_end(); I != E; ++I)
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if (*I == NextBB)
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return true;
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return false;
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}
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/// InitialFunctionScan - Do the initial scan of the function, building up
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/// information about the sizes of each block, the location of all the water,
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/// and finding all of the constant pool users.
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void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
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const std::vector<MachineInstr*> &CPEMIs) {
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for (MachineFunction::iterator MBBI = Fn.begin(), E = Fn.end();
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MBBI != E; ++MBBI) {
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MachineBasicBlock &MBB = *MBBI;
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// If this block doesn't fall through into the next MBB, then this is
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// 'water' that a constant pool island could be placed.
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if (!BBHasFallthrough(&MBB))
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WaterList.push_back(&MBB);
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unsigned MBBSize = 0;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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// Add instruction size to MBBSize.
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MBBSize += GetInstSize(I);
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int Opc = I->getOpcode();
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if (TII->isBranch(Opc)) {
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bool isCond = false;
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unsigned Bits = 0;
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unsigned Scale = 1;
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int UOpc = Opc;
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switch (Opc) {
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default:
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continue; // Ignore JT branches
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case ARM::Bcc:
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isCond = true;
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UOpc = ARM::B;
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// Fallthrough
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case ARM::B:
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Bits = 24;
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Scale = 4;
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break;
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case ARM::tBcc:
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isCond = true;
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UOpc = ARM::tB;
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Bits = 8;
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Scale = 2;
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break;
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case ARM::tB:
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Bits = 11;
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Scale = 2;
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break;
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}
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unsigned MaxDisp = (1 << (Bits-1)) * Scale;
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ImmBranches.push_back(ImmBranch(I, MaxDisp, isCond, UOpc));
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}
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// Scan the instructions for constant pool operands.
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for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
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if (I->getOperand(op).isConstantPoolIndex()) {
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// We found one. The addressing mode tells us the max displacement
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// from the PC that this instruction permits.
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unsigned MaxOffs = 0;
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// Basic size info comes from the TSFlags field.
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unsigned TSFlags = I->getInstrDescriptor()->TSFlags;
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switch (TSFlags & ARMII::AddrModeMask) {
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default:
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// Constant pool entries can reach anything.
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if (I->getOpcode() == ARM::CONSTPOOL_ENTRY)
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continue;
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assert(0 && "Unknown addressing mode for CP reference!");
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case ARMII::AddrMode1: // AM1: 8 bits << 2
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MaxOffs = 1 << (8+2); // Taking the address of a CP entry.
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break;
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case ARMII::AddrMode2:
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MaxOffs = 1 << 12; // +-offset_12
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break;
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case ARMII::AddrMode3:
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MaxOffs = 1 << 8; // +-offset_8
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break;
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// addrmode4 has no immediate offset.
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case ARMII::AddrMode5:
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MaxOffs = 1 << (8+2); // +-(offset_8*4)
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break;
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case ARMII::AddrModeT1:
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MaxOffs = 1 << 5;
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break;
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case ARMII::AddrModeT2:
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MaxOffs = 1 << (5+1);
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break;
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case ARMII::AddrModeT4:
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MaxOffs = 1 << (5+2);
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break;
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case ARMII::AddrModeTs:
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MaxOffs = 1 << (8+2);
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break;
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}
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// Remember that this is a user of a CP entry.
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MachineInstr *CPEMI =CPEMIs[I->getOperand(op).getConstantPoolIndex()];
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CPUsers.push_back(CPUser(I, CPEMI, MaxOffs));
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// Instructions can only use one CP entry, don't bother scanning the
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// rest of the operands.
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break;
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}
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}
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BBSizes.push_back(MBBSize);
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}
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}
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/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
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static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
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unsigned JTI) DISABLE_INLINE;
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static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
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unsigned JTI) {
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return JT[JTI].MBBs.size();
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}
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/// GetInstSize - Return the size of the specified MachineInstr.
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///
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unsigned ARMConstantIslands::GetInstSize(MachineInstr *MI) const {
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// Basic size info comes from the TSFlags field.
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unsigned TSFlags = MI->getInstrDescriptor()->TSFlags;
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switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
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default:
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// If this machine instr is an inline asm, measure it.
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if (MI->getOpcode() == ARM::INLINEASM)
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return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
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assert(0 && "Unknown or unset size field for instr!");
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break;
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case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
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case ARMII::Size4Bytes: return 4; // Arm instruction.
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case ARMII::Size2Bytes: return 2; // Thumb instruction.
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case ARMII::SizeSpecial: {
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switch (MI->getOpcode()) {
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case ARM::CONSTPOOL_ENTRY:
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// If this machine instr is a constant pool entry, its size is recorded as
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// operand #2.
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return MI->getOperand(2).getImm();
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case ARM::BR_JTr:
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case ARM::BR_JTm:
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case ARM::BR_JTadd: {
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// These are jumptable branches, i.e. a branch followed by an inlined
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// jumptable. The size is 4 + 4 * number of entries.
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unsigned JTI = MI->getOperand(MI->getNumOperands()-2).getJumpTableIndex();
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const MachineFunction *MF = MI->getParent()->getParent();
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MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
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const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
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assert(JTI < JT.size());
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return getNumJTEntries(JT, JTI) * 4 + 4;
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}
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default:
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// Otherwise, pseudo-instruction sizes are zero.
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return 0;
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}
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}
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}
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}
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/// GetOffsetOf - Return the current offset of the specified machine instruction
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/// from the start of the function. This offset changes as stuff is moved
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/// around inside the function.
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unsigned ARMConstantIslands::GetOffsetOf(MachineInstr *MI) const {
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MachineBasicBlock *MBB = MI->getParent();
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// The offset is composed of two things: the sum of the sizes of all MBB's
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// before this instruction's block, and the offset from the start of the block
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// it is in.
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unsigned Offset = 0;
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// Sum block sizes before MBB.
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for (unsigned BB = 0, e = MBB->getNumber(); BB != e; ++BB)
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Offset += BBSizes[BB];
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// Sum instructions before MI in MBB.
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for (MachineBasicBlock::iterator I = MBB->begin(); ; ++I) {
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assert(I != MBB->end() && "Didn't find MI in its own basic block?");
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if (&*I == MI) return Offset;
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Offset += GetInstSize(I);
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}
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}
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/// GetOffsetOf - Return the current offset of the specified machine BB
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/// from the start of the function. This offset changes as stuff is moved
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/// around inside the function.
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unsigned ARMConstantIslands::GetOffsetOf(MachineBasicBlock *MBB) const {
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// Sum block sizes before MBB.
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unsigned Offset = 0;
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for (unsigned BB = 0, e = MBB->getNumber(); BB != e; ++BB)
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Offset += BBSizes[BB];
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return Offset;
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}
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/// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
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/// ID.
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static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
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const MachineBasicBlock *RHS) {
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return LHS->getNumber() < RHS->getNumber();
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}
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/// UpdateForInsertedWaterBlock - When a block is newly inserted into the
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/// machine function, it upsets all of the block numbers. Renumber the blocks
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/// and update the arrays that parallel this numbering.
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void ARMConstantIslands::UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
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// Renumber the MBB's to keep them consequtive.
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NewBB->getParent()->RenumberBlocks(NewBB);
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// Insert a size into BBSizes to align it properly with the (newly
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// renumbered) block numbers.
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BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
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// Next, update WaterList. Specifically, we need to add NewMBB as having
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// available water after it.
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std::vector<MachineBasicBlock*>::iterator IP =
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std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
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CompareMBBNumbers);
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WaterList.insert(IP, NewBB);
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}
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/// Split the basic block containing MI into two blocks, which are joined by
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/// an unconditional branch. Update datastructures and renumber blocks to
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/// account for this change.
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void ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) {
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MachineBasicBlock *OrigBB = MI->getParent();
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const ARMFunctionInfo *AFI = OrigBB->getParent()->getInfo<ARMFunctionInfo>();
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bool isThumb = AFI->isThumbFunction();
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// Create a new MBB for the code after the OrigBB.
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MachineBasicBlock *NewBB = new MachineBasicBlock(OrigBB->getBasicBlock());
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MachineFunction::iterator MBBI = OrigBB; ++MBBI;
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OrigBB->getParent()->getBasicBlockList().insert(MBBI, NewBB);
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// Splice the instructions starting with MI over to NewBB.
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NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
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// Add an unconditional branch from OrigBB to NewBB.
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BuildMI(OrigBB, TII->get(isThumb ? ARM::tB : ARM::B)).addMBB(NewBB);
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NumSplit++;
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// Update the CFG. All succs of OrigBB are now succs of NewBB.
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while (!OrigBB->succ_empty()) {
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MachineBasicBlock *Succ = *OrigBB->succ_begin();
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OrigBB->removeSuccessor(Succ);
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NewBB->addSuccessor(Succ);
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// This pass should be run after register allocation, so there should be no
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// PHI nodes to update.
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assert((Succ->empty() || Succ->begin()->getOpcode() != TargetInstrInfo::PHI)
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&& "PHI nodes should be eliminated by now!");
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}
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// OrigBB branches to NewBB.
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OrigBB->addSuccessor(NewBB);
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// Update internal data structures to account for the newly inserted MBB.
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UpdateForInsertedWaterBlock(NewBB);
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// Figure out how large the first NewMBB is.
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unsigned NewBBSize = 0;
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for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end();
|
|
I != E; ++I)
|
|
NewBBSize += GetInstSize(I);
|
|
|
|
// Set the size of NewBB in BBSizes.
|
|
BBSizes[NewBB->getNumber()] = NewBBSize;
|
|
|
|
// We removed instructions from UserMBB, subtract that off from its size.
|
|
// Add 2 or 4 to the block to count the unconditional branch we added to it.
|
|
BBSizes[OrigBB->getNumber()] -= NewBBSize - (isThumb ? 2 : 4);
|
|
}
|
|
|
|
/// HandleConstantPoolUser - Analyze the specified user, checking to see if it
|
|
/// is out-of-range. If so, pick it up the constant pool value and move it some
|
|
/// place in-range.
|
|
bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &Fn, CPUser &U){
|
|
MachineInstr *UserMI = U.MI;
|
|
MachineInstr *CPEMI = U.CPEMI;
|
|
|
|
unsigned UserOffset = GetOffsetOf(UserMI);
|
|
unsigned CPEOffset = GetOffsetOf(CPEMI);
|
|
|
|
DEBUG(std::cerr << "User of CPE#" << CPEMI->getOperand(0).getImm()
|
|
<< " max delta=" << U.MaxDisp
|
|
<< " at offset " << int(UserOffset-CPEOffset) << "\t"
|
|
<< *UserMI);
|
|
|
|
// Check to see if the CPE is already in-range.
|
|
if (UserOffset < CPEOffset) {
|
|
// User before the CPE.
|
|
if (CPEOffset-UserOffset <= U.MaxDisp)
|
|
return false;
|
|
} else {
|
|
if (UserOffset-CPEOffset <= U.MaxDisp)
|
|
return false;
|
|
}
|
|
|
|
|
|
// Solution guaranteed to work: split the user's MBB right before the user and
|
|
// insert a clone the CPE into the newly created water.
|
|
|
|
// If the user isn't at the start of its MBB, or if there is a fall-through
|
|
// into the user's MBB, split the MBB before the User.
|
|
MachineBasicBlock *UserMBB = UserMI->getParent();
|
|
if (&UserMBB->front() != UserMI ||
|
|
UserMBB == &Fn.front() || // entry MBB of function.
|
|
BBHasFallthrough(prior(MachineFunction::iterator(UserMBB)))) {
|
|
// TODO: Search for the best place to split the code. In practice, using
|
|
// loop nesting information to insert these guys outside of loops would be
|
|
// sufficient.
|
|
SplitBlockBeforeInstr(UserMI);
|
|
|
|
// UserMI's BB may have changed.
|
|
UserMBB = UserMI->getParent();
|
|
}
|
|
|
|
// Okay, we know we can put an island before UserMBB now, do it!
|
|
MachineBasicBlock *NewIsland = new MachineBasicBlock();
|
|
Fn.getBasicBlockList().insert(UserMBB, NewIsland);
|
|
|
|
// Update internal data structures to account for the newly inserted MBB.
|
|
UpdateForInsertedWaterBlock(NewIsland);
|
|
|
|
// Now that we have an island to add the CPE to, clone the original CPE and
|
|
// add it to the island.
|
|
unsigned ID = NextUID++;
|
|
unsigned CPI = CPEMI->getOperand(1).getConstantPoolIndex();
|
|
unsigned Size = CPEMI->getOperand(2).getImm();
|
|
|
|
// Build a new CPE for this user.
|
|
U.CPEMI = BuildMI(NewIsland, TII->get(ARM::CONSTPOOL_ENTRY))
|
|
.addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
|
|
|
|
// Increase the size of the island block to account for the new entry.
|
|
BBSizes[NewIsland->getNumber()] += Size;
|
|
|
|
// Finally, change the CPI in the instruction operand to be ID.
|
|
for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
|
|
if (UserMI->getOperand(i).isConstantPoolIndex()) {
|
|
UserMI->getOperand(i).setConstantPoolIndex(ID);
|
|
break;
|
|
}
|
|
|
|
DEBUG(std::cerr << " Moved CPE to #" << ID << " CPI=" << CPI << "\t"
|
|
<< *UserMI);
|
|
|
|
|
|
return true;
|
|
}
|
|
|
|
/// FixUpImmediateBranch - Fix up immediate branches whose destination is too
|
|
/// far away to fit in its displacement field. If it is a conditional branch,
|
|
/// then it is converted to an inverse conditional branch + an unconditional
|
|
/// branch to the destination. If it is an unconditional branch, then it is
|
|
/// converted to a branch to a branch.
|
|
bool
|
|
ARMConstantIslands::FixUpImmediateBranch(MachineFunction &Fn, ImmBranch &Br) {
|
|
MachineInstr *MI = Br.MI;
|
|
MachineBasicBlock *DestBB = MI->getOperand(0).getMachineBasicBlock();
|
|
|
|
unsigned BrOffset = GetOffsetOf(MI);
|
|
unsigned DestOffset = GetOffsetOf(DestBB);
|
|
|
|
// Check to see if the destination BB is in range.
|
|
if (BrOffset < DestOffset) {
|
|
if (DestOffset - BrOffset < Br.MaxDisp)
|
|
return false;
|
|
} else {
|
|
if (BrOffset - DestOffset <= Br.MaxDisp)
|
|
return false;
|
|
}
|
|
|
|
if (!Br.isCond) {
|
|
// Unconditional branch. We have to insert a branch somewhere to perform
|
|
// a two level branch (branch to branch). FIXME: not yet implemented.
|
|
assert(false && "Can't handle unconditional branch yet!");
|
|
return false;
|
|
}
|
|
|
|
// Otherwise, add a unconditional branch to the destination and
|
|
// invert the branch condition to jump over it:
|
|
// blt L1
|
|
// =>
|
|
// bge L2
|
|
// b L1
|
|
// L2:
|
|
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImmedValue();
|
|
CC = ARMCC::getOppositeCondition(CC);
|
|
|
|
// If the branch is at the end of its MBB and that has a fall-through block,
|
|
// direct the updated conditional branch to the fall-through block. Otherwise,
|
|
// split the MBB before the next instruction.
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
if (&MBB->back() != MI || !BBHasFallthrough(MBB))
|
|
SplitBlockBeforeInstr(MI);
|
|
MachineBasicBlock *NextBB = next(MachineFunction::iterator(MBB));
|
|
|
|
// Insert a unconditional branch and replace the conditional branch.
|
|
// Also update the ImmBranch as well as adding a new entry for the new branch.
|
|
BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB).addImm((unsigned)CC);
|
|
Br.MI = &MBB->back();
|
|
BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB);
|
|
unsigned MaxDisp = (Br.UncondBr == ARM::tB) ? (1<<10)*2 : (1<<23)*4;
|
|
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
|
|
MI->eraseFromParent();
|
|
|
|
// Increase the size of MBB to account for the new unconditional branch.
|
|
BBSizes[MBB->getNumber()] += GetInstSize(&MBB->back());
|
|
return true;
|
|
}
|