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https://github.com/c64scene-ar/llvm-6502.git
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a0ea0539e3
1. Various asm printer bug. 2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8
263 lines
8.5 KiB
C++
Executable File
263 lines
8.5 KiB
C++
Executable File
//===-- X86IntelAsmPrinter.cpp - Convert X86 LLVM code to Intel assembly --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to Intel format assembly language.
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// This printer is the output mechanism used by `llc'.
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//
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//===----------------------------------------------------------------------===//
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#include "X86IntelAsmPrinter.h"
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#include "X86.h"
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#include "llvm/Module.h"
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#include "llvm/Assembly/Writer.h"
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#include "llvm/Support/Mangler.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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using namespace x86;
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/// runOnMachineFunction - This uses the printMachineInstruction()
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/// method to print assembly for each instruction.
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///
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bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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SetupMachineFunction(MF);
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O << "\n\n";
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// Print out constants referenced by the function
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EmitConstantPool(MF.getConstantPool());
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// Print out labels for the function.
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SwitchSection("\t.text\n", MF.getFunction());
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EmitAlignment(4);
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O << "\t.globl\t" << CurrentFnName << "\n";
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if (HasDotTypeDotSizeDirective)
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O << "\t.type\t" << CurrentFnName << ", @function\n";
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O << CurrentFnName << ":\n";
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// Print out code for the function.
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block if there are any predecessors.
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if (I->pred_begin() != I->pred_end())
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O << PrivateGlobalPrefix << "BB" << CurrentFnName << "_" << I->getNumber()
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<< ":\t"
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<< CommentString << " " << I->getBasicBlock()->getName() << "\n";
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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O << "\t";
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printMachineInstruction(II);
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}
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}
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// We didn't modify anything.
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return false;
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}
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void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
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unsigned char value = MI->getOperand(Op).getImmedValue();
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assert(value <= 7 && "Invalid ssecc argument!");
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switch (value) {
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case 0: O << "eq"; break;
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case 1: O << "lt"; break;
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case 2: O << "le"; break;
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case 3: O << "unord"; break;
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case 4: O << "neq"; break;
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case 5: O << "nlt"; break;
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case 6: O << "nle"; break;
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case 7: O << "ord"; break;
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}
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}
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void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
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const char *Modifier) {
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const MRegisterInfo &RI = *TM.getRegisterInfo();
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (Value *V = MO.getVRegValueOrNull()) {
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O << "<" << V->getName() << ">";
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return;
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}
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// FALLTHROUGH
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case MachineOperand::MO_MachineRegister:
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if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
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// Bug Workaround: See note in Printer::doInitialization about %.
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O << "%" << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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case MachineOperand::MO_SignExtendedImmed:
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_MachineBasicBlock: {
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MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
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O << PrivateGlobalPrefix << "BB"
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<< Mang->getValueName(MBBOp->getParent()->getFunction())
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<< "_" << MBBOp->getNumber () << "\t# "
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<< MBBOp->getBasicBlock ()->getName ();
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return;
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}
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case MachineOperand::MO_PCRelativeDisp:
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assert(0 && "Shouldn't use addPCDisp() when building X86 MachineInstrs");
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abort ();
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return;
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case MachineOperand::MO_GlobalAddress: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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bool isMemOp = Modifier && !strcmp(Modifier, "mem");
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if (!isMemOp && !isCallOp) O << "OFFSET ";
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if (forDarwin && TM.getRelocationModel() != Reloc::Static) {
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GlobalValue *GV = MO.getGlobal();
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std::string Name = Mang->getValueName(GV);
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if (!isMemOp && !isCallOp) O << '$';
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// Link-once, External, or Weakly-linked global variables need
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// non-lazily-resolved stubs
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if (GV->isExternal() || GV->hasWeakLinkage() ||
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GV->hasLinkOnceLinkage()) {
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// Dynamically-resolved functions need a stub for the function.
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if (isCallOp && isa<Function>(GV) && cast<Function>(GV)->isExternal()) {
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FnStubs.insert(Name);
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O << "L" << Name << "$stub";
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} else {
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GVStubs.insert(Name);
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O << "L" << Name << "$non_lazy_ptr";
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}
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} else {
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O << Mang->getValueName(GV);
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}
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if (!isCallOp && TM.getRelocationModel() == Reloc::PIC)
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O << "-\"L" << getFunctionNumber() << "$pb\"";
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} else
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O << Mang->getValueName(MO.getGlobal());
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int Offset = MO.getOffset();
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if (Offset > 0)
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O << " + " << Offset;
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else if (Offset < 0)
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O << Offset;
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return;
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}
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case MachineOperand::MO_ExternalSymbol: {
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bool isCallOp = Modifier && !strcmp(Modifier, "call");
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if (isCallOp && forDarwin && TM.getRelocationModel() != Reloc::Static) {
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std::string Name(GlobalPrefix);
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Name += MO.getSymbolName();
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FnStubs.insert(Name);
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O << "L" << Name << "$stub";
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return;
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}
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if (!isCallOp) O << "OFFSET ";
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O << GlobalPrefix << MO.getSymbolName();
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return;
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}
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default:
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O << "<unknown operand type>"; return;
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}
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}
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void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op){
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assert(isMem(MI, Op) && "Invalid memory reference!");
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const MachineOperand &BaseReg = MI->getOperand(Op);
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int ScaleVal = MI->getOperand(Op+1).getImmedValue();
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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const MachineOperand &DispSpec = MI->getOperand(Op+3);
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if (BaseReg.isFrameIndex()) {
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O << "[frame slot #" << BaseReg.getFrameIndex();
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if (DispSpec.getImmedValue())
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O << " + " << DispSpec.getImmedValue();
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O << "]";
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return;
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} else if (BaseReg.isConstantPoolIndex()) {
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O << "[" << PrivateGlobalPrefix << "CPI" << getFunctionNumber() << "_"
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<< BaseReg.getConstantPoolIndex();
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if (forDarwin && TM.getRelocationModel() == Reloc::PIC)
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O << "-\"L" << getFunctionNumber() << "$pb\"";
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if (IndexReg.getReg()) {
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O << " + ";
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if (ScaleVal != 1)
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O << ScaleVal << "*";
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printOp(IndexReg);
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}
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if (DispSpec.getImmedValue())
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O << " + " << DispSpec.getImmedValue();
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O << "]";
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return;
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}
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O << "[";
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bool NeedPlus = false;
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if (BaseReg.getReg()) {
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printOp(BaseReg, "mem");
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NeedPlus = true;
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}
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if (IndexReg.getReg()) {
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if (NeedPlus) O << " + ";
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if (ScaleVal != 1)
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O << ScaleVal << "*";
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printOp(IndexReg);
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NeedPlus = true;
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}
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if (DispSpec.isGlobalAddress()) {
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if (NeedPlus)
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O << " + ";
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printOp(DispSpec, "mem");
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} else {
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int DispVal = DispSpec.getImmedValue();
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if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
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if (NeedPlus)
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if (DispVal > 0)
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O << " + ";
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else {
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O << " - ";
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DispVal = -DispVal;
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}
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O << DispVal;
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}
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}
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O << "]";
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}
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void X86IntelAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
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O << "\"L" << getFunctionNumber() << "$pb\"\n";
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O << "\"L" << getFunctionNumber() << "$pb\":";
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}
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/// printMachineInstruction -- Print out a single X86 LLVM instruction
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/// MI in Intel syntax to the current output stream.
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///
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void X86IntelAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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++EmittedInsts;
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// Call the autogenerated instruction printer routines.
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printInstruction(MI);
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}
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bool X86IntelAsmPrinter::doInitialization(Module &M) {
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X86SharedAsmPrinter::doInitialization(M);
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// Tell gas we are outputting Intel syntax (not AT&T syntax) assembly.
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//
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// Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an
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// instruction as a reference to the register named sp, and if you try to
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// reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased
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// before being looked up in the symbol table. This creates spurious
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// `undefined symbol' errors when linking. Workaround: Do not use `noprefix'
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// mode, and decorate all register names with percent signs.
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O << "\t.intel_syntax\n";
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return false;
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}
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// Include the auto-generated portion of the assembly writer.
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#include "X86GenAsmWriter1.inc"
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