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e7147dba73
it. It's been assumed up til now that it would be in its immediate successor. However, this isn't necessarily the case. It could be in one of its successor's successors. Modify the code to more thoroughly check for an 'eh.selector' call in successors. It only looks at a successor if we get there as a result of an unconditional branch. Testcase ObjC/exceptions-4.m in r126968. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126969 91177308-0d34-0410-b5e6-96231b3b80d8
225 lines
7.6 KiB
C++
225 lines
7.6 KiB
C++
//===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements routines for translating functions from LLVM IR into
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// Machine IR.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
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#define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
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#include "llvm/InlineAsm.h"
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#include "llvm/Instructions.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallVector.h"
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#ifndef NDEBUG
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#include "llvm/ADT/SmallSet.h"
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#endif
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Support/CallSite.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <vector>
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namespace llvm {
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class AllocaInst;
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class BasicBlock;
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class CallInst;
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class Function;
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class GlobalVariable;
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class Instruction;
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class MachineInstr;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineModuleInfo;
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class MachineRegisterInfo;
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class TargetLowering;
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class Value;
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//===--------------------------------------------------------------------===//
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/// FunctionLoweringInfo - This contains information that is global to a
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/// function that is used when lowering a region of the function.
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///
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class FunctionLoweringInfo {
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public:
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const TargetLowering &TLI;
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const Function *Fn;
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MachineFunction *MF;
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MachineRegisterInfo *RegInfo;
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/// CanLowerReturn - true iff the function's return value can be lowered to
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/// registers.
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bool CanLowerReturn;
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/// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
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/// allocated to hold a pointer to the hidden sret parameter.
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unsigned DemoteRegister;
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/// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
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DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
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/// ValueMap - Since we emit code for the function a basic block at a time,
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/// we must remember which virtual registers hold the values for
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/// cross-basic-block values.
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DenseMap<const Value*, unsigned> ValueMap;
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/// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
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/// the entry block. This allows the allocas to be efficiently referenced
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/// anywhere in the function.
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DenseMap<const AllocaInst*, int> StaticAllocaMap;
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/// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
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DenseMap<const Argument*, int> ByValArgFrameIndexMap;
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/// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
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/// function arguments that are inserted after scheduling is completed.
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SmallVector<MachineInstr*, 8> ArgDbgValues;
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/// RegFixups - Registers which need to be replaced after isel is done.
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DenseMap<unsigned, unsigned> RegFixups;
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/// MBB - The current block.
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MachineBasicBlock *MBB;
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/// MBB - The current insert position inside the current block.
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MachineBasicBlock::iterator InsertPt;
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#ifndef NDEBUG
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SmallSet<const Instruction *, 8> CatchInfoLost;
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SmallSet<const Instruction *, 8> CatchInfoFound;
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#endif
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struct LiveOutInfo {
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unsigned NumSignBits : 31;
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bool IsValid : 1;
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APInt KnownOne, KnownZero;
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LiveOutInfo() : NumSignBits(0), IsValid(true), KnownOne(1, 0),
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KnownZero(1, 0) {}
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};
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/// VisitedBBs - The set of basic blocks visited thus far by instruction
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/// selection.
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DenseSet<const BasicBlock*> VisitedBBs;
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/// PHINodesToUpdate - A list of phi instructions whose operand list will
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/// be updated after processing the current basic block.
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/// TODO: This isn't per-function state, it's per-basic-block state. But
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/// there's no other convenient place for it to live right now.
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std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
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explicit FunctionLoweringInfo(const TargetLowering &TLI);
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/// set - Initialize this FunctionLoweringInfo with the given Function
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/// and its associated MachineFunction.
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///
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void set(const Function &Fn, MachineFunction &MF);
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/// clear - Clear out all the function-specific state. This returns this
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/// FunctionLoweringInfo to an empty state, ready to be used for a
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/// different function.
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void clear();
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/// isExportedInst - Return true if the specified value is an instruction
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/// exported from its block.
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bool isExportedInst(const Value *V) {
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return ValueMap.count(V);
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}
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unsigned CreateReg(EVT VT);
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unsigned CreateRegs(const Type *Ty);
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unsigned InitializeRegForValue(const Value *V) {
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unsigned &R = ValueMap[V];
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assert(R == 0 && "Already initialized this value register!");
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return R = CreateRegs(V->getType());
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}
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/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
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/// register is a PHI destination and the PHI's LiveOutInfo is not valid.
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const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
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if (!LiveOutRegInfo.inBounds(Reg))
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return NULL;
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const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
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if (!LOI->IsValid)
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return NULL;
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return LOI;
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}
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/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
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/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
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/// the register's LiveOutInfo is for a smaller bit width, it is extended to
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/// the larger bit width by zero extension. The bit width must be no smaller
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/// than the LiveOutInfo's existing bit width.
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const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
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/// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
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void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
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const APInt &KnownZero, const APInt &KnownOne) {
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// Only install this information if it tells us something.
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if (NumSignBits == 1 && KnownZero == 0 && KnownOne == 0)
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return;
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LiveOutRegInfo.grow(Reg);
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LiveOutInfo &LOI = LiveOutRegInfo[Reg];
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LOI.NumSignBits = NumSignBits;
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LOI.KnownOne = KnownOne;
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LOI.KnownZero = KnownZero;
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}
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/// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
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/// register based on the LiveOutInfo of its operands.
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void ComputePHILiveOutRegInfo(const PHINode*);
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/// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
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/// called when a block is visited before all of its predecessors.
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void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
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// PHIs with no uses have no ValueMap entry.
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DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
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if (It == ValueMap.end())
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return;
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unsigned Reg = It->second;
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LiveOutRegInfo.grow(Reg);
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LiveOutRegInfo[Reg].IsValid = false;
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}
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/// setByValArgumentFrameIndex - Record frame index for the byval
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/// argument.
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void setByValArgumentFrameIndex(const Argument *A, int FI);
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/// getByValArgumentFrameIndex - Get frame index for the byval argument.
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int getByValArgumentFrameIndex(const Argument *A);
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private:
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/// LiveOutRegInfo - Information about live out vregs.
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IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
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};
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/// AddCatchInfo - Extract the personality and type infos from an eh.selector
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/// call, and add them to the specified machine basic block.
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void AddCatchInfo(const CallInst &I,
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MachineModuleInfo *MMI, MachineBasicBlock *MBB);
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/// CopyCatchInfo - Copy catch information from SuccBB (or one of its
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/// successors) to LPad.
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void CopyCatchInfo(const BasicBlock *SuccBB, const BasicBlock *LPad,
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MachineModuleInfo *MMI, FunctionLoweringInfo &FLI);
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} // end namespace llvm
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#endif
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