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https://github.com/c64scene-ar/llvm-6502.git
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a10756ee65
This new version is much more aggressive about doing "full" reduction in cases where it reduces register pressure, and also more aggressive about rewriting induction variables to count down (or up) to zero when doing so reduces register pressure. It currently uses fairly simplistic algorithms for finding reuse opportunities, but it introduces a new framework allows it to combine multiple strategies at once to form hybrid solutions, instead of doing all full-reduction or all base+index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94061 91177308-0d34-0410-b5e6-96231b3b80d8
51 lines
2.0 KiB
LLVM
51 lines
2.0 KiB
LLVM
; RUN: llc < %s -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of reloads omited}
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target datalayout = "e-p:32:32:32"
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target triple = "i386-apple-darwin9.6"
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%struct.constraintVCGType = type { i32, i32, i32, i32 }
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%struct.nodeVCGType = type { %struct.constraintVCGType*, i32, i32, i32, %struct.constraintVCGType*, i32, i32, i32 }
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define fastcc void @SCC_DFSBelowVCG(%struct.nodeVCGType* %VCG, i32 %net, i32 %label) nounwind {
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entry:
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%0 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 5 ; <i32*> [#uses=2]
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%1 = load i32* %0, align 4 ; <i32> [#uses=1]
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%2 = icmp eq i32 %1, 0 ; <i1> [#uses=1]
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br i1 %2, label %bb5, label %bb.nph3
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bb.nph3: ; preds = %entry
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%3 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 4 ; <%struct.constraintVCGType**> [#uses=1]
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br label %bb
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bb: ; preds = %bb3, %bb.nph3
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%s.02 = phi i32 [ 0, %bb.nph3 ], [ %12, %bb3 ] ; <i32> [#uses=2]
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%4 = load %struct.constraintVCGType** %3, align 4 ; <%struct.constraintVCGType*> [#uses=1]
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%5 = icmp eq i32 0, 0 ; <i1> [#uses=1]
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br i1 %5, label %bb1, label %bb3
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bb1: ; preds = %bb
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%6 = getelementptr %struct.constraintVCGType* %4, i32 %s.02, i32 0 ; <i32*> [#uses=1]
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%7 = load i32* %6, align 4 ; <i32> [#uses=2]
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%8 = getelementptr %struct.nodeVCGType* %VCG, i32 %7, i32 7 ; <i32*> [#uses=1]
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%9 = load i32* %8, align 4 ; <i32> [#uses=1]
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%10 = icmp eq i32 %9, 0 ; <i1> [#uses=1]
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br i1 %10, label %bb2, label %bb3
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bb2: ; preds = %bb1
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%11 = getelementptr %struct.nodeVCGType* %VCG, i32 %7, i32 4 ; <%struct.constraintVCGType**> [#uses=0]
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br label %bb.i
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bb.i: ; preds = %bb.i, %bb2
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br label %bb.i
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bb3: ; preds = %bb1, %bb
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%12 = add i32 %s.02, 1 ; <i32> [#uses=2]
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%13 = load i32* %0, align 4 ; <i32> [#uses=1]
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%14 = icmp ugt i32 %13, %12 ; <i1> [#uses=1]
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br i1 %14, label %bb, label %bb5
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bb5: ; preds = %bb3, %entry
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%15 = getelementptr %struct.nodeVCGType* %VCG, i32 %net, i32 6 ; <i32*> [#uses=1]
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store i32 %label, i32* %15, align 4
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ret void
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}
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