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dc6eaa4125
This gets us closer to being able to remove LiveVariables entirely which is where dead instructions are currently tagged as such. Reviewed by Jakob Olesen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210132 91177308-0d34-0410-b5e6-96231b3b80d8
422 lines
16 KiB
C++
422 lines
16 KiB
C++
//===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass. Given some numbering of
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// each the machine instructions (in this implemention depth-first order) an
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// interval [i, j) is said to be a live interval for register v if there is no
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// instruction with number j' > j such that v is live at j' and there is no
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// instruction with number i' < i such that v is live at i'. In this
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// implementation intervals can have holes, i.e. an interval might look like
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// [1,20), [50,65), [1000,1001).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/Support/Allocator.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <cmath>
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#include <iterator>
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namespace llvm {
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class AliasAnalysis;
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class BitVector;
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class BlockFrequency;
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class LiveRangeCalc;
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class LiveVariables;
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class MachineDominatorTree;
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class MachineLoopInfo;
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class TargetRegisterInfo;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class VirtRegMap;
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class MachineBlockFrequencyInfo;
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class LiveIntervals : public MachineFunctionPass {
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MachineFunction* MF;
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MachineRegisterInfo* MRI;
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const TargetMachine* TM;
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const TargetRegisterInfo* TRI;
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const TargetInstrInfo* TII;
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AliasAnalysis *AA;
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SlotIndexes* Indexes;
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MachineDominatorTree *DomTree;
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LiveRangeCalc *LRCalc;
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/// Special pool allocator for VNInfo's (LiveInterval val#).
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///
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VNInfo::Allocator VNInfoAllocator;
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/// Live interval pointers for all the virtual registers.
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IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
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/// RegMaskSlots - Sorted list of instructions with register mask operands.
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/// Always use the 'r' slot, RegMasks are normal clobbers, not early
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/// clobbers.
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SmallVector<SlotIndex, 8> RegMaskSlots;
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/// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
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/// pointer to the corresponding register mask. This pointer can be
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/// recomputed as:
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///
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/// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
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/// unsigned OpNum = findRegMaskOperand(MI);
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/// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
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///
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/// This is kept in a separate vector partly because some standard
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/// libraries don't support lower_bound() with mixed objects, partly to
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/// improve locality when searching in RegMaskSlots.
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/// Also see the comment in LiveInterval::find().
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SmallVector<const uint32_t*, 8> RegMaskBits;
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/// For each basic block number, keep (begin, size) pairs indexing into the
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/// RegMaskSlots and RegMaskBits arrays.
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/// Note that basic block numbers may not be layout contiguous, that's why
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/// we can't just keep track of the first register mask in each basic
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/// block.
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SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
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/// Keeps a live range set for each register unit to track fixed physreg
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/// interference.
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SmallVector<LiveRange*, 0> RegUnitRanges;
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public:
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static char ID; // Pass identification, replacement for typeid
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LiveIntervals();
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virtual ~LiveIntervals();
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// Calculate the spill weight to assign to a single instruction.
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static float getSpillWeight(bool isDef, bool isUse,
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const MachineBlockFrequencyInfo *MBFI,
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const MachineInstr *Instr);
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LiveInterval &getInterval(unsigned Reg) {
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if (hasInterval(Reg))
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return *VirtRegIntervals[Reg];
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else
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return createAndComputeVirtRegInterval(Reg);
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}
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const LiveInterval &getInterval(unsigned Reg) const {
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return const_cast<LiveIntervals*>(this)->getInterval(Reg);
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}
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bool hasInterval(unsigned Reg) const {
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return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
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}
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// Interval creation.
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LiveInterval &createEmptyInterval(unsigned Reg) {
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assert(!hasInterval(Reg) && "Interval already exists!");
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VirtRegIntervals.grow(Reg);
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VirtRegIntervals[Reg] = createInterval(Reg);
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return *VirtRegIntervals[Reg];
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}
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LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) {
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LiveInterval &LI = createEmptyInterval(Reg);
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computeVirtRegInterval(LI);
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return LI;
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}
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// Interval removal.
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void removeInterval(unsigned Reg) {
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delete VirtRegIntervals[Reg];
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VirtRegIntervals[Reg] = nullptr;
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}
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/// Given a register and an instruction, adds a live segment from that
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/// instruction to the end of its MBB.
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LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
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MachineInstr* startInst);
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/// shrinkToUses - After removing some uses of a register, shrink its live
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/// range to just the remaining uses. This method does not compute reaching
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/// defs for new uses, and it doesn't remove dead defs.
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/// Dead PHIDef values are marked as unused.
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/// New dead machine instructions are added to the dead vector.
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/// Return true if the interval may have been separated into multiple
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/// connected components.
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bool shrinkToUses(LiveInterval *li,
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SmallVectorImpl<MachineInstr*> *dead = nullptr);
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/// \brief Walk the values in the given interval and compute which ones
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/// are dead. Dead values are not deleted, however:
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/// - Dead PHIDef values are marked as unused.
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/// - New dead machine instructions are added to the dead vector.
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/// - CanSeparate is set to true if the interval may have been separated
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/// into multiple connected components.
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void computeDeadValues(LiveInterval *li,
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LiveRange &LR,
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bool *CanSeparate,
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SmallVectorImpl<MachineInstr*> *dead);
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/// extendToIndices - Extend the live range of LI to reach all points in
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/// Indices. The points in the Indices array must be jointly dominated by
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/// existing defs in LI. PHI-defs are added as needed to maintain SSA form.
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///
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/// If a SlotIndex in Indices is the end index of a basic block, LI will be
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/// extended to be live out of the basic block.
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///
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/// See also LiveRangeCalc::extend().
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void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices);
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/// pruneValue - If an LI value is live at Kill, prune its live range by
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/// removing any liveness reachable from Kill. Add live range end points to
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/// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
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/// value's live range.
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///
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/// Calling pruneValue() and extendToIndices() can be used to reconstruct
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/// SSA form after adding defs to a virtual register.
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void pruneValue(LiveInterval *LI, SlotIndex Kill,
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SmallVectorImpl<SlotIndex> *EndPoints);
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SlotIndexes *getSlotIndexes() const {
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return Indexes;
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}
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AliasAnalysis *getAliasAnalysis() const {
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return AA;
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}
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/// isNotInMIMap - returns true if the specified machine instr has been
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/// removed or was never entered in the map.
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bool isNotInMIMap(const MachineInstr* Instr) const {
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return !Indexes->hasIndex(Instr);
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}
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/// Returns the base index of the given instruction.
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SlotIndex getInstructionIndex(const MachineInstr *instr) const {
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return Indexes->getInstructionIndex(instr);
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}
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/// Returns the instruction associated with the given index.
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MachineInstr* getInstructionFromIndex(SlotIndex index) const {
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return Indexes->getInstructionFromIndex(index);
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}
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/// Return the first index in the given basic block.
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SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
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return Indexes->getMBBStartIdx(mbb);
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}
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/// Return the last index in the given basic block.
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SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
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return Indexes->getMBBEndIdx(mbb);
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}
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bool isLiveInToMBB(const LiveRange &LR,
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const MachineBasicBlock *mbb) const {
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return LR.liveAt(getMBBStartIdx(mbb));
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}
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bool isLiveOutOfMBB(const LiveRange &LR,
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const MachineBasicBlock *mbb) const {
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return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
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}
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MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
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return Indexes->getMBBFromIndex(index);
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}
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void insertMBBInMaps(MachineBasicBlock *MBB) {
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Indexes->insertMBBInMaps(MBB);
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assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
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"Blocks must be added in order.");
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RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
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}
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SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
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return Indexes->insertMachineInstrInMaps(MI);
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}
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void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
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MachineBasicBlock::iterator E) {
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for (MachineBasicBlock::iterator I = B; I != E; ++I)
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Indexes->insertMachineInstrInMaps(I);
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}
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void RemoveMachineInstrFromMaps(MachineInstr *MI) {
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Indexes->removeMachineInstrFromMaps(MI);
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}
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void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
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Indexes->replaceMachineInstrInMaps(MI, NewMI);
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}
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bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
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SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
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return Indexes->findLiveInMBBs(Start, End, MBBs);
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}
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VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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void releaseMemory() override;
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/// runOnMachineFunction - pass entry point
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bool runOnMachineFunction(MachineFunction&) override;
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/// print - Implement the dump method.
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void print(raw_ostream &O, const Module* = nullptr) const override;
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/// intervalIsInOneMBB - If LI is confined to a single basic block, return
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/// a pointer to that block. If LI is live in to or out of any block,
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/// return NULL.
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MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
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/// Returns true if VNI is killed by any PHI-def values in LI.
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/// This may conservatively return true to avoid expensive computations.
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bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
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/// addKillFlags - Add kill flags to any instruction that kills a virtual
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/// register.
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void addKillFlags(const VirtRegMap*);
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/// handleMove - call this method to notify LiveIntervals that
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/// instruction 'mi' has been moved within a basic block. This will update
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/// the live intervals for all operands of mi. Moves between basic blocks
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/// are not supported.
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///
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/// \param UpdateFlags Update live intervals for nonallocatable physregs.
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void handleMove(MachineInstr* MI, bool UpdateFlags = false);
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/// moveIntoBundle - Update intervals for operands of MI so that they
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/// begin/end on the SlotIndex for BundleStart.
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///
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/// \param UpdateFlags Update live intervals for nonallocatable physregs.
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///
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/// Requires MI and BundleStart to have SlotIndexes, and assumes
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/// existing liveness is accurate. BundleStart should be the first
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/// instruction in the Bundle.
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void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart,
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bool UpdateFlags = false);
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/// repairIntervalsInRange - Update live intervals for instructions in a
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/// range of iterators. It is intended for use after target hooks that may
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/// insert or remove instructions, and is only efficient for a small number
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/// of instructions.
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///
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/// OrigRegs is a vector of registers that were originally used by the
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/// instructions in the range between the two iterators.
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///
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/// Currently, the only only changes that are supported are simple removal
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/// and addition of uses.
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void repairIntervalsInRange(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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ArrayRef<unsigned> OrigRegs);
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// Register mask functions.
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//
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// Machine instructions may use a register mask operand to indicate that a
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// large number of registers are clobbered by the instruction. This is
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// typically used for calls.
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//
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// For compile time performance reasons, these clobbers are not recorded in
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// the live intervals for individual physical registers. Instead,
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// LiveIntervalAnalysis maintains a sorted list of instructions with
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// register mask operands.
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/// getRegMaskSlots - Returns a sorted array of slot indices of all
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/// instructions with register mask operands.
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ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
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/// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
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/// instructions with register mask operands in the basic block numbered
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/// MBBNum.
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ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
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std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
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return getRegMaskSlots().slice(P.first, P.second);
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}
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/// getRegMaskBits() - Returns an array of register mask pointers
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/// corresponding to getRegMaskSlots().
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ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
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/// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
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/// to getRegMaskSlotsInBlock(MBBNum).
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ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
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std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
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return getRegMaskBits().slice(P.first, P.second);
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}
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/// checkRegMaskInterference - Test if LI is live across any register mask
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/// instructions, and compute a bit mask of physical registers that are not
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/// clobbered by any of them.
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///
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/// Returns false if LI doesn't cross any register mask instructions. In
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/// that case, the bit vector is not filled in.
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bool checkRegMaskInterference(LiveInterval &LI,
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BitVector &UsableRegs);
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// Register unit functions.
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//
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// Fixed interference occurs when MachineInstrs use physregs directly
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// instead of virtual registers. This typically happens when passing
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// arguments to a function call, or when instructions require operands in
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// fixed registers.
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//
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// Each physreg has one or more register units, see MCRegisterInfo. We
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// track liveness per register unit to handle aliasing registers more
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// efficiently.
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/// getRegUnit - Return the live range for Unit.
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/// It will be computed if it doesn't exist.
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LiveRange &getRegUnit(unsigned Unit) {
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LiveRange *LR = RegUnitRanges[Unit];
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if (!LR) {
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// Compute missing ranges on demand.
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RegUnitRanges[Unit] = LR = new LiveRange();
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computeRegUnitRange(*LR, Unit);
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}
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return *LR;
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}
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/// getCachedRegUnit - Return the live range for Unit if it has already
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/// been computed, or NULL if it hasn't been computed yet.
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LiveRange *getCachedRegUnit(unsigned Unit) {
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return RegUnitRanges[Unit];
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}
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const LiveRange *getCachedRegUnit(unsigned Unit) const {
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return RegUnitRanges[Unit];
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}
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private:
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/// Compute live intervals for all virtual registers.
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void computeVirtRegs();
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/// Compute RegMaskSlots and RegMaskBits.
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void computeRegMasks();
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static LiveInterval* createInterval(unsigned Reg);
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void printInstrs(raw_ostream &O) const;
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void dumpInstrs() const;
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void computeLiveInRegUnits();
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void computeRegUnitRange(LiveRange&, unsigned Unit);
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void computeVirtRegInterval(LiveInterval&);
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class HMEditor;
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};
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} // End llvm namespace
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#endif
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