mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d04a8d4b33
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.4 KiB
C++
72 lines
2.4 KiB
C++
//===-- MSP430TargetMachine.cpp - Define TargetMachine for MSP430 ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the MSP430 target.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430TargetMachine.h"
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#include "MSP430.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeMSP430Target() {
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// Register the target.
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RegisterTargetMachine<MSP430TargetMachine> X(TheMSP430Target);
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}
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MSP430TargetMachine::MSP430TargetMachine(const Target &T,
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StringRef TT,
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StringRef CPU,
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StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS),
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// FIXME: Check DataLayout string.
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DL("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
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InstrInfo(*this), TLInfo(*this), TSInfo(*this),
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FrameLowering(Subtarget), STTI(&TLInfo), VTTI(&TLInfo) { }
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namespace {
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/// MSP430 Code Generator Pass Configuration Options.
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class MSP430PassConfig : public TargetPassConfig {
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public:
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MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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MSP430TargetMachine &getMSP430TargetMachine() const {
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return getTM<MSP430TargetMachine>();
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}
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virtual bool addInstSelector();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new MSP430PassConfig(this, PM);
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}
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bool MSP430PassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
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return false;
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}
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bool MSP430PassConfig::addPreEmitPass() {
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// Must run branch selection immediately preceding the asm printer.
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addPass(createMSP430BranchSelectionPass());
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return false;
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}
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