mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-11 23:05:31 +00:00
d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
525 B
LLVM
25 lines
525 B
LLVM
; RUN: llc < %s -march=ptx32 | FileCheck %s
|
|
|
|
define ptx_device void @test_bra_direct() {
|
|
; CHECK: bra $L__BB0_1;
|
|
entry:
|
|
br label %loop
|
|
loop:
|
|
br label %loop
|
|
}
|
|
|
|
define ptx_device i32 @test_bra_cond_direct(i32 %x, i32 %y) {
|
|
entry:
|
|
; CHECK: setp.le.u32 p0, r[[R0:[0-9]+]], r[[R1:[0-9]+]]
|
|
%p = icmp ugt i32 %x, %y
|
|
; CHECK-NEXT: @p0 bra
|
|
; CHECK-NOT: bra
|
|
br i1 %p, label %clause.if, label %clause.else
|
|
clause.if:
|
|
; CHECK: mov.u32 r{{[0-9]+}}, r[[R0]]
|
|
ret i32 %x
|
|
clause.else:
|
|
; CHECK: mov.u32 r{{[0-9]+}}, r[[R1]]
|
|
ret i32 %y
|
|
}
|