mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-01 19:29:22 +00:00
VSX is an ISA extension supported on the POWER7 and later cores that enhances floating-point vector and scalar capabilities. Among other things, this adds <2 x double> support and generally helps to reduce register pressure. The interesting part of this ISA feature is the register configuration: there are 64 new 128-bit vector registers, the 32 of which are super-registers of the existing 32 scalar floating-point registers, and the second 32 of which overlap with the 32 Altivec vector registers. This makes things like vector insertion and extraction tricky: this can be free but only if we force a restriction to the right register subclass when needed. A new "minipass" PPCVSXCopy takes care of this (although it could do a more-optimal job of it; see the comment about unnecessary copies below). Please note that, currently, VSX is not enabled by default when targeting anything because it is not yet ready for that. The assembler and disassembler are fully implemented and tested. However: - CodeGen support causes miscompiles; test-suite runtime failures: MultiSource/Benchmarks/FreeBench/distray/distray MultiSource/Benchmarks/McCat/08-main/main MultiSource/Benchmarks/Olden/voronoi/voronoi MultiSource/Benchmarks/mafft/pairlocalalign MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4 SingleSource/Benchmarks/CoyoteBench/almabench SingleSource/Benchmarks/Misc/matmul_f64_4x4 - The lowering currently falls back to using Altivec instructions far more than it should. Worse, there are some things that are scalarized through the stack that shouldn't be. - A lot of unnecessary copies make it past the optimizers, and this needs to be fixed. - Many more regression tests are needed. Normally, I'd fix these things prior to committing, but there are some students and other contributors who would like to work this, and so it makes sense to move this development process upstream where it can be subject to the regular code-review procedures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
235 lines
7.4 KiB
C++
235 lines
7.4 KiB
C++
//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements the PPC specific subclass of TargetSubtargetInfo.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "PPCSubtarget.h"
|
|
#include "PPC.h"
|
|
#include "PPCRegisterInfo.h"
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
|
#include "llvm/CodeGen/MachineScheduler.h"
|
|
#include "llvm/IR/Attributes.h"
|
|
#include "llvm/IR/Function.h"
|
|
#include "llvm/IR/GlobalValue.h"
|
|
#include "llvm/Support/Host.h"
|
|
#include "llvm/Support/TargetRegistry.h"
|
|
#include "llvm/Target/TargetMachine.h"
|
|
#include <cstdlib>
|
|
|
|
#define GET_SUBTARGETINFO_TARGET_DESC
|
|
#define GET_SUBTARGETINFO_CTOR
|
|
#include "PPCGenSubtargetInfo.inc"
|
|
|
|
using namespace llvm;
|
|
|
|
PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
|
|
const std::string &FS, bool is64Bit,
|
|
CodeGenOpt::Level OptLevel)
|
|
: PPCGenSubtargetInfo(TT, CPU, FS)
|
|
, IsPPC64(is64Bit)
|
|
, TargetTriple(TT) {
|
|
initializeEnvironment();
|
|
|
|
std::string FullFS = FS;
|
|
|
|
// At -O2 and above, track CR bits as individual registers.
|
|
if (OptLevel >= CodeGenOpt::Default) {
|
|
if (!FullFS.empty())
|
|
FullFS = "+crbits," + FullFS;
|
|
else
|
|
FullFS = "+crbits";
|
|
}
|
|
|
|
resetSubtargetFeatures(CPU, FullFS);
|
|
}
|
|
|
|
/// SetJITMode - This is called to inform the subtarget info that we are
|
|
/// producing code for the JIT.
|
|
void PPCSubtarget::SetJITMode() {
|
|
// JIT mode doesn't want lazy resolver stubs, it knows exactly where
|
|
// everything is. This matters for PPC64, which codegens in PIC mode without
|
|
// stubs.
|
|
HasLazyResolverStubs = false;
|
|
|
|
// Calls to external functions need to use indirect calls
|
|
IsJITCodeModel = true;
|
|
}
|
|
|
|
void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
|
|
AttributeSet FnAttrs = MF->getFunction()->getAttributes();
|
|
Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
|
|
"target-cpu");
|
|
Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
|
|
"target-features");
|
|
std::string CPU =
|
|
!CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
|
|
std::string FS =
|
|
!FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
|
|
if (!FS.empty()) {
|
|
initializeEnvironment();
|
|
resetSubtargetFeatures(CPU, FS);
|
|
}
|
|
}
|
|
|
|
void PPCSubtarget::initializeEnvironment() {
|
|
StackAlignment = 16;
|
|
DarwinDirective = PPC::DIR_NONE;
|
|
HasMFOCRF = false;
|
|
Has64BitSupport = false;
|
|
Use64BitRegs = false;
|
|
UseCRBits = false;
|
|
HasAltivec = false;
|
|
HasQPX = false;
|
|
HasVSX = false;
|
|
HasFCPSGN = false;
|
|
HasFSQRT = false;
|
|
HasFRE = false;
|
|
HasFRES = false;
|
|
HasFRSQRTE = false;
|
|
HasFRSQRTES = false;
|
|
HasRecipPrec = false;
|
|
HasSTFIWX = false;
|
|
HasLFIWAX = false;
|
|
HasFPRND = false;
|
|
HasFPCVT = false;
|
|
HasISEL = false;
|
|
HasPOPCNTD = false;
|
|
HasLDBRX = false;
|
|
IsBookE = false;
|
|
DeprecatedMFTB = false;
|
|
DeprecatedDST = false;
|
|
HasLazyResolverStubs = false;
|
|
IsJITCodeModel = false;
|
|
}
|
|
|
|
void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
|
|
// Determine default and user specified characteristics
|
|
std::string CPUName = CPU;
|
|
if (CPUName.empty())
|
|
CPUName = "generic";
|
|
#if (defined(__APPLE__) || defined(__linux__)) && \
|
|
(defined(__ppc__) || defined(__powerpc__))
|
|
if (CPUName == "generic")
|
|
CPUName = sys::getHostCPUName();
|
|
#endif
|
|
|
|
// Initialize scheduling itinerary for the specified CPU.
|
|
InstrItins = getInstrItineraryForCPU(CPUName);
|
|
|
|
// Make sure 64-bit features are available when CPUname is generic
|
|
std::string FullFS = FS;
|
|
|
|
// If we are generating code for ppc64, verify that options make sense.
|
|
if (IsPPC64) {
|
|
Has64BitSupport = true;
|
|
// Silently force 64-bit register use on ppc64.
|
|
Use64BitRegs = true;
|
|
if (!FullFS.empty())
|
|
FullFS = "+64bit," + FullFS;
|
|
else
|
|
FullFS = "+64bit";
|
|
}
|
|
|
|
// Parse features string.
|
|
ParseSubtargetFeatures(CPUName, FullFS);
|
|
|
|
// If the user requested use of 64-bit regs, but the cpu selected doesn't
|
|
// support it, ignore.
|
|
if (use64BitRegs() && !has64BitSupport())
|
|
Use64BitRegs = false;
|
|
|
|
// Set up darwin-specific properties.
|
|
if (isDarwin())
|
|
HasLazyResolverStubs = true;
|
|
|
|
// QPX requires a 32-byte aligned stack. Note that we need to do this if
|
|
// we're compiling for a BG/Q system regardless of whether or not QPX
|
|
// is enabled because external functions will assume this alignment.
|
|
if (hasQPX() || isBGQ())
|
|
StackAlignment = 32;
|
|
|
|
// Determine endianness.
|
|
IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
|
|
}
|
|
|
|
/// hasLazyResolverStub - Return true if accesses to the specified global have
|
|
/// to go through a dyld lazy resolution stub. This means that an extra load
|
|
/// is required to get the address of the global.
|
|
bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
|
|
const TargetMachine &TM) const {
|
|
// We never have stubs if HasLazyResolverStubs=false or if in static mode.
|
|
if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
|
|
return false;
|
|
// If symbol visibility is hidden, the extra load is not needed if
|
|
// the symbol is definitely defined in the current translation unit.
|
|
bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
|
|
if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
|
|
return false;
|
|
return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
|
|
GV->hasCommonLinkage() || isDecl;
|
|
}
|
|
|
|
bool PPCSubtarget::enablePostRAScheduler(
|
|
CodeGenOpt::Level OptLevel,
|
|
TargetSubtargetInfo::AntiDepBreakMode& Mode,
|
|
RegClassVector& CriticalPathRCs) const {
|
|
Mode = TargetSubtargetInfo::ANTIDEP_ALL;
|
|
|
|
CriticalPathRCs.clear();
|
|
|
|
if (isPPC64())
|
|
CriticalPathRCs.push_back(&PPC::G8RCRegClass);
|
|
else
|
|
CriticalPathRCs.push_back(&PPC::GPRCRegClass);
|
|
|
|
return OptLevel >= CodeGenOpt::Default;
|
|
}
|
|
|
|
// Embedded cores need aggressive scheduling (and some others also benefit).
|
|
static bool needsAggressiveScheduling(unsigned Directive) {
|
|
switch (Directive) {
|
|
default: return false;
|
|
case PPC::DIR_440:
|
|
case PPC::DIR_A2:
|
|
case PPC::DIR_E500mc:
|
|
case PPC::DIR_E5500:
|
|
case PPC::DIR_PWR7:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
bool PPCSubtarget::enableMachineScheduler() const {
|
|
// Enable MI scheduling for the embedded cores.
|
|
// FIXME: Enable this for all cores (some additional modeling
|
|
// may be necessary).
|
|
return needsAggressiveScheduling(DarwinDirective);
|
|
}
|
|
|
|
void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
|
|
MachineInstr *begin,
|
|
MachineInstr *end,
|
|
unsigned NumRegionInstrs) const {
|
|
if (needsAggressiveScheduling(DarwinDirective)) {
|
|
Policy.OnlyTopDown = false;
|
|
Policy.OnlyBottomUp = false;
|
|
}
|
|
|
|
// Spilling is generally expensive on all PPC cores, so always enable
|
|
// register-pressure tracking.
|
|
Policy.ShouldTrackPressure = true;
|
|
}
|
|
|
|
bool PPCSubtarget::useAA() const {
|
|
// Use AA during code generation for the embedded cores.
|
|
return needsAggressiveScheduling(DarwinDirective);
|
|
}
|
|
|