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48575f6ea7
difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
236 lines
7.1 KiB
C++
236 lines
7.1 KiB
C++
//===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARM specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMSubtarget.h"
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#include "ARMGenSubtarget.inc"
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#include "llvm/GlobalValue.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/SmallVector.h"
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using namespace llvm;
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static cl::opt<bool>
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ReserveR9("arm-reserve-r9", cl::Hidden,
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cl::desc("Reserve R9, making it unavailable as GPR"));
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static cl::opt<bool>
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UseMOVT("arm-use-movt",
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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StrictAlign("arm-strict-align", cl::Hidden,
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cl::desc("Disallow all unaligned memory accesses"));
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ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
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bool isT)
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: ARMArchVersion(V4)
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, ARMProcFamily(Others)
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, ARMFPUType(None)
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, UseNEONForSinglePrecisionFP(false)
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, SlowFPVMLx(false)
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, SlowFPBrcc(false)
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, IsThumb(isT)
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, ThumbMode(Thumb1)
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, NoARM(false)
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, PostRAScheduler(false)
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, IsR9Reserved(ReserveR9)
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, UseMovt(UseMOVT)
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, HasFP16(false)
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, HasD16(false)
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, HasHardwareDivide(false)
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, HasT2ExtractPack(false)
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, HasDataBarrier(false)
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, Pref32BitThumb(false)
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, HasMPExtension(false)
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, FPOnlySP(false)
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, AllowsUnalignedMem(false)
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, stackAlignment(4)
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, CPUString("generic")
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, TargetType(isELF) // Default to ELF unless otherwise specified.
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, TargetABI(ARM_ABI_APCS) {
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// Default to soft float ABI
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if (FloatABIType == FloatABI::Default)
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FloatABIType = FloatABI::Soft;
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// Determine default and user specified characteristics
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// When no arch is specified either by CPU or by attributes, make the default
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// ARMv4T.
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const char *ARMArchFeature = "";
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if (CPUString == "generic" && (FS.empty() || FS == "generic")) {
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ARMArchVersion = V4T;
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ARMArchFeature = ",+v4t";
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}
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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unsigned Len = TT.length();
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unsigned Idx = 0;
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if (Len >= 5 && TT.substr(0, 4) == "armv")
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Idx = 4;
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else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
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IsThumb = true;
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if (Len >= 7 && TT[5] == 'v')
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Idx = 6;
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}
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if (Idx) {
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unsigned SubVer = TT[Idx];
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if (SubVer >= '7' && SubVer <= '9') {
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ARMArchVersion = V7A;
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ARMArchFeature = ",+v7a";
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if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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ARMArchVersion = V7M;
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ARMArchFeature = ",+v7m";
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}
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} else if (SubVer == '6') {
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ARMArchVersion = V6;
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ARMArchFeature = ",+v6";
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
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ARMArchVersion = V6T2;
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ARMArchFeature = ",+v6t2";
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}
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} else if (SubVer == '5') {
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ARMArchVersion = V5T;
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ARMArchFeature = ",+v5t";
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
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ARMArchVersion = V5TE;
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ARMArchFeature = ",+v5te";
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}
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} else if (SubVer == '4') {
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if (Len >= Idx+2 && TT[Idx+1] == 't') {
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ARMArchVersion = V4T;
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ARMArchFeature = ",+v4t";
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} else {
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ARMArchVersion = V4;
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ARMArchFeature = "";
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}
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}
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}
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if (Len >= 10) {
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if (TT.find("-darwin") != std::string::npos)
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// arm-darwin
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TargetType = isDarwin;
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}
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if (TT.find("eabi") != std::string::npos)
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TargetABI = ARM_ABI_AAPCS;
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// Parse features string. If the first entry in FS (the CPU) is missing,
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// insert the architecture feature derived from the target triple. This is
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// important for setting features that are implied based on the architecture
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// version.
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std::string FSWithArch;
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if (FS.empty())
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FSWithArch = std::string(ARMArchFeature);
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else if (FS.find(',') == 0)
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FSWithArch = std::string(ARMArchFeature) + FS;
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else
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FSWithArch = FS;
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CPUString = ParseSubtargetFeatures(FSWithArch, CPUString);
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// Thumb2 implies at least V6T2.
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if (ARMArchVersion >= V6T2)
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ThumbMode = Thumb2;
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else if (ThumbMode >= Thumb2)
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ARMArchVersion = V6T2;
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if (isAAPCS_ABI())
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stackAlignment = 8;
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if (isTargetDarwin())
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IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
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if (!isThumb() || hasThumb2())
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PostRAScheduler = true;
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// v6+ may or may not support unaligned mem access depending on the system
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// configuration.
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if (!StrictAlign && hasV6Ops() && isTargetDarwin())
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AllowsUnalignedMem = true;
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}
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/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
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bool
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ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
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Reloc::Model RelocM) const {
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if (RelocM == Reloc::Static)
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return false;
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// Materializable GVs (in JIT lazy compilation mode) do not require an extra
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// load from stub.
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bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
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if (!isTargetDarwin()) {
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return false;
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return true;
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} else {
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if (RelocM == Reloc::PIC_) {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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if (isDecl || GV->hasCommonLinkage())
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// Hidden $non_lazy_ptr reference.
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return true;
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return false;
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} else {
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return false;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return true;
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}
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}
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return false;
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}
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unsigned ARMSubtarget::getMispredictionPenalty() const {
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// If we have a reasonable estimate of the pipeline depth, then we can
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// estimate the penalty of a misprediction based on that.
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if (isCortexA8())
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return 13;
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else if (isCortexA9())
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return 8;
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// Otherwise, just return a sensible default.
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return 10;
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}
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bool ARMSubtarget::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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TargetSubtarget::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = TargetSubtarget::ANTIDEP_CRITICAL;
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(&ARM::GPRRegClass);
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return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
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}
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