mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
4.1 KiB
LLVM
92 lines
4.1 KiB
LLVM
; RUN: opt %s -sroa -verify -S -o - | FileCheck %s
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; From:
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; struct prog_src_register {
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; unsigned : 4;
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; int Index : 12 + 1;
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; unsigned : 12;
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; unsigned : 4;
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; int : 12 + 1
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; } src_reg_for_float() {
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; struct prog_src_register a;
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; memset(&a, 0, sizeof(a));
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; int local = a.Index;
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; return a;
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; }
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; ModuleID = 'pr22495.c'
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; When SROA is creating new smaller allocas, it may add padding.
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;
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; There should be no debug info for the padding.
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; CHECK-NOT: DW_OP_bit_piece offset=56
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; CHECK: [ DW_TAG_expression ] [DW_OP_bit_piece offset=32, size=24]
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; CHECK-NOT: DW_OP_bit_piece offset=56
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; CHECK: [ DW_TAG_expression ] [DW_OP_bit_piece offset=0, size=32]
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; CHECK-NOT: DW_OP_bit_piece offset=56
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%struct.prog_src_register = type { i32, i24 }
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; Function Attrs: nounwind
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define i64 @src_reg_for_float() #0 {
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entry:
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%retval = alloca %struct.prog_src_register, align 4
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%a = alloca %struct.prog_src_register, align 4
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%local = alloca i32, align 4
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call void @llvm.dbg.declare(metadata %struct.prog_src_register* %a, metadata !16, metadata !17), !dbg !18
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%0 = bitcast %struct.prog_src_register* %a to i8*, !dbg !19
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call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 8, i32 4, i1 false), !dbg !19
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call void @llvm.dbg.declare(metadata i32* %local, metadata !20, metadata !17), !dbg !21
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%1 = bitcast %struct.prog_src_register* %a to i32*, !dbg !21
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%bf.load = load i32, i32* %1, align 4, !dbg !21
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%bf.shl = shl i32 %bf.load, 15, !dbg !21
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%bf.ashr = ashr i32 %bf.shl, 19, !dbg !21
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store i32 %bf.ashr, i32* %local, align 4, !dbg !21
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%2 = bitcast %struct.prog_src_register* %retval to i8*, !dbg !22
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%3 = bitcast %struct.prog_src_register* %a to i8*, !dbg !22
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 8, i32 4, i1 false), !dbg !22
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%4 = bitcast %struct.prog_src_register* %retval to i64*, !dbg !22
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%5 = load i64, i64* %4, align 1, !dbg !22
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ret i64 %5, !dbg !22
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}
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; Function Attrs: nounwind readnone
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declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
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; Function Attrs: nounwind
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #2
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; Function Attrs: nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!13, !14}
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!llvm.ident = !{!15}
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!0 = !{!"0x11\0012\00clang version 3.7.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/<stdin>] [DW_LANG_C99]
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!1 = !{!"<stdin>", !""}
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!2 = !{}
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!3 = !{!4}
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!4 = !{!"0x2e\00src_reg_for_float\00src_reg_for_float\00\007\000\001\000\000\000\000\007", !5, !6, !7, null, i64 ()* @src_reg_for_float, null, null, !2} ; [ DW_TAG_subprogram ] [line 7] [def] [src_reg_for_float]
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!5 = !{!"pr22495.c", !""}
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!6 = !{!"0x29", !5} ; [ DW_TAG_file_type ] [/pr22495.c]
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!7 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
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!8 = !{!9}
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!9 = !{!"0x13\00prog_src_register\001\0064\0032\000\000\000", !5, null, null, !10, null, null, null} ; [ DW_TAG_structure_type ] [prog_src_register] [line 1, size 64, align 32, offset 0] [def] [from ]
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!10 = !{!11}
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!11 = !{!"0xd\00Index\003\0013\0032\004\000", !5, !9, !12} ; [ DW_TAG_member ] [Index] [line 3, size 13, align 32, offset 4] [from int]
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!12 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
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!13 = !{i32 2, !"Dwarf Version", i32 4}
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!14 = !{i32 2, !"Debug Info Version", i32 2}
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!15 = !{!"clang version 3.7.0 "}
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!16 = !{!"0x100\00a\008\000", !4, !6, !9} ; [ DW_TAG_auto_variable ] [a] [line 8]
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!17 = !{!"0x102"} ; [ DW_TAG_expression ]
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!18 = !MDLocation(line: 8, scope: !4)
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!19 = !MDLocation(line: 9, scope: !4)
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!20 = !{!"0x100\00local\0010\000", !4, !6, !12} ; [ DW_TAG_auto_variable ] [local] [line 10]
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!21 = !MDLocation(line: 10, scope: !4)
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!22 = !MDLocation(line: 11, scope: !4)
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