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d84561bf69
In a previous iteration of the pass, we would try to compensate for writeback by updating later instructions and/or inserting a SUBS to reset the base register if necessary. Since such a SUBS sets the condition flags it's not generally safe to do this. For now, only merge LDR/STRs if there is no writeback to the base register (LDM that loads into the base register) or the base register is killed by one of the merged instructions. These cases are clear wins both in terms of instruction count and performance. Also add three new test cases, and update the existing ones accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215729 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
705 B
LLVM
22 lines
705 B
LLVM
; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs %s -o - | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-none--eabi"
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%struct.S = type { i32, i32 }
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@s = common global %struct.S zeroinitializer, align 4
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define i32 @f() {
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entry:
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; CHECK-LABEL: f:
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; CHECK: ldm r[[BASE:[0-9]]],
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; CHECK-NEXT-NOT: subs r[[BASE]]
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%0 = load i32* getelementptr inbounds (%struct.S* @s, i32 0, i32 0), align 4
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%1 = load i32* getelementptr inbounds (%struct.S* @s, i32 0, i32 1), align 4
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%cmp = icmp sgt i32 %0, %1
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%2 = sub i32 0, %1
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%cond.p = select i1 %cmp, i32 %1, i32 %2
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%cond = add i32 %cond.p, %0
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ret i32 %cond
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}
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