mirror of
https://github.com/c64scene-ar/llvm-6502.git
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This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
1065 lines
38 KiB
C++
1065 lines
38 KiB
C++
//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of a target
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// register file for a code generator. It uses instances of the Register,
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// RegisterAliases, and RegisterClass classes to gather this information.
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//
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//===----------------------------------------------------------------------===//
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#include "RegisterInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "CodeGenRegisters.h"
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#include "SequenceToOffsetTable.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/Format.h"
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#include <algorithm>
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#include <set>
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using namespace llvm;
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// runEnums - Print out enum values for all of the registers.
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void RegisterInfoEmitter::runEnums(raw_ostream &OS,
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CodeGenTarget &Target, CodeGenRegBank &Bank) {
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const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
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// Register enums are stored as uint16_t in the tables. Make sure we'll fit.
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assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
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std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
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EmitSourceFileHeader("Target Register Enum Values", OS);
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OS << "\n#ifdef GET_REGINFO_ENUM\n";
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OS << "#undef GET_REGINFO_ENUM\n";
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OS << "namespace llvm {\n\n";
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OS << "class MCRegisterClass;\n"
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<< "extern const MCRegisterClass " << Namespace
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<< "MCRegisterClasses[];\n\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n NoRegister,\n";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i)
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OS << " " << Registers[i]->getName() << " = " <<
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Registers[i]->EnumValue << ",\n";
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assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
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"Register enum value mismatch!");
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OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
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OS << "};\n";
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if (!Namespace.empty())
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OS << "}\n";
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ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
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if (!RegisterClasses.empty()) {
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// RegisterClass enums are stored as uint16_t in the tables.
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assert(RegisterClasses.size() <= 0xffff &&
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"Too many register classes to fit in tables");
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OS << "\n// Register classes\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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if (i) OS << ",\n";
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OS << " " << RegisterClasses[i]->getName() << "RegClassID";
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OS << " = " << i;
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}
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OS << "\n };\n";
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if (!Namespace.empty())
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OS << "}\n";
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}
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const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
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// If the only definition is the default NoRegAltName, we don't need to
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// emit anything.
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if (RegAltNameIndices.size() > 1) {
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OS << "\n// Register alternate name indices\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n";
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for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
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OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
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OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
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OS << "};\n";
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if (!Namespace.empty())
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OS << "}\n";
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}
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ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
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if (!SubRegIndices.empty()) {
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OS << "\n// Subregister indices\n";
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std::string Namespace =
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SubRegIndices[0]->getNamespace();
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n NoSubRegister,\n";
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for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
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OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
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OS << " NUM_TARGET_NAMED_SUBREGS\n};\n";
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if (!Namespace.empty())
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OS << "}\n";
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}
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OS << "} // End llvm namespace \n";
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OS << "#endif // GET_REGINFO_ENUM\n\n";
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}
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void RegisterInfoEmitter::
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EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
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const std::string &ClassName) {
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unsigned NumRCs = RegBank.getRegClasses().size();
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unsigned NumSets = RegBank.getNumRegPressureSets();
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OS << "/// Get the weight in units of pressure for this register class.\n"
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<< "const RegClassWeight &" << ClassName << "::\n"
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<< "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
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<< " static const RegClassWeight RCWeightTable[] = {\n";
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for (unsigned i = 0, e = NumRCs; i != e; ++i) {
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const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
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const CodeGenRegister::Set &Regs = RC.getMembers();
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if (Regs.empty())
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OS << " {0, 0";
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else {
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std::vector<unsigned> RegUnits;
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RC.buildRegUnitSet(RegUnits);
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OS << " {" << (*Regs.begin())->getWeight(RegBank)
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<< ", " << RegBank.getRegUnitSetWeight(RegUnits);
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}
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OS << "}, \t// " << RC.getName() << "\n";
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}
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OS << " {0, 0} };\n"
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<< " return RCWeightTable[RC->getID()];\n"
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<< "}\n\n";
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OS << "\n"
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<< "// Get the number of dimensions of register pressure.\n"
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<< "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
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<< " return " << NumSets << ";\n}\n\n";
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OS << "// Get the name of this register unit pressure set.\n"
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<< "const char *" << ClassName << "::\n"
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<< "getRegPressureSetName(unsigned Idx) const {\n"
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<< " static const char *PressureNameTable[] = {\n";
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for (unsigned i = 0; i < NumSets; ++i ) {
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OS << " \"" << RegBank.getRegPressureSet(i).Name << "\",\n";
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}
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OS << " 0 };\n"
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<< " return PressureNameTable[Idx];\n"
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<< "}\n\n";
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OS << "// Get the register unit pressure limit for this dimension.\n"
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<< "// This limit must be adjusted dynamically for reserved registers.\n"
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<< "unsigned " << ClassName << "::\n"
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<< "getRegPressureSetLimit(unsigned Idx) const {\n"
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<< " static const unsigned PressureLimitTable[] = {\n";
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for (unsigned i = 0; i < NumSets; ++i ) {
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const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
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OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units)
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<< ", \t// " << i << ": " << RegUnits.Name << "\n";
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}
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OS << " 0 };\n"
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<< " return PressureLimitTable[Idx];\n"
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<< "}\n\n";
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OS << "/// Get the dimensions of register pressure "
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<< "impacted by this register class.\n"
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<< "/// Returns a -1 terminated array of pressure set IDs\n"
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<< "const int* " << ClassName << "::\n"
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<< "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"
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<< " static const int RCSetsTable[] = {\n ";
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std::vector<unsigned> RCSetStarts(NumRCs);
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for (unsigned i = 0, StartIdx = 0, e = NumRCs; i != e; ++i) {
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RCSetStarts[i] = StartIdx;
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ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
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for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
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PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
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OS << *PSetI << ", ";
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++StartIdx;
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}
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OS << "-1, \t// " << RegBank.getRegClasses()[i]->getName() << "\n ";
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++StartIdx;
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}
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OS << "-1 };\n";
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OS << " static const unsigned RCSetStartTable[] = {\n ";
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for (unsigned i = 0, e = NumRCs; i != e; ++i) {
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OS << RCSetStarts[i] << ",";
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}
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OS << "0 };\n"
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<< " unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
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<< " return &RCSetsTable[SetListStart];\n"
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<< "}\n\n";
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}
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void
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RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
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const std::vector<CodeGenRegister*> &Regs,
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bool isCtor) {
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// Collect all information about dwarf register numbers
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typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
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DwarfRegNumsMapTy DwarfRegNums;
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// First, just pull all provided information to the map
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unsigned maxLength = 0;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *Reg = Regs[i]->TheDef;
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std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
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maxLength = std::max((size_t)maxLength, RegNums.size());
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if (DwarfRegNums.count(Reg))
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PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
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getQualifiedName(Reg) + "specified multiple times");
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DwarfRegNums[Reg] = RegNums;
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}
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if (!maxLength)
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return;
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// Now we know maximal length of number list. Append -1's, where needed
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for (DwarfRegNumsMapTy::iterator
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I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
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for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
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I->second.push_back(-1);
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std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
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OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
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// Emit reverse information about the dwarf register numbers.
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for (unsigned j = 0; j < 2; ++j) {
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for (unsigned i = 0, e = maxLength; i != e; ++i) {
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OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
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OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
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OS << i << "Dwarf2L[]";
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if (!isCtor) {
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OS << " = {\n";
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// Store the mapping sorted by the LLVM reg num so lookup can be done
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// with a binary search.
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std::map<uint64_t, Record*> Dwarf2LMap;
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for (DwarfRegNumsMapTy::iterator
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I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
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int DwarfRegNo = I->second[i];
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if (DwarfRegNo < 0)
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continue;
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Dwarf2LMap[DwarfRegNo] = I->first;
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}
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for (std::map<uint64_t, Record*>::iterator
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I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
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OS << " { " << I->first << "U, " << getQualifiedName(I->second)
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<< " },\n";
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OS << "};\n";
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} else {
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OS << ";\n";
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}
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// We have to store the size in a const global, it's used in multiple
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// places.
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OS << "extern const unsigned " << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
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if (!isCtor)
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OS << " = sizeof(" << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
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<< "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
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else
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OS << ";\n\n";
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}
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}
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *Reg = Regs[i]->TheDef;
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const RecordVal *V = Reg->getValue("DwarfAlias");
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if (!V || !V->getValue())
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continue;
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DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
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Record *Alias = DI->getDef();
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DwarfRegNums[Reg] = DwarfRegNums[Alias];
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}
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// Emit information about the dwarf register numbers.
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for (unsigned j = 0; j < 2; ++j) {
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for (unsigned i = 0, e = maxLength; i != e; ++i) {
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OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
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OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
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OS << i << "L2Dwarf[]";
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if (!isCtor) {
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OS << " = {\n";
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// Store the mapping sorted by the Dwarf reg num so lookup can be done
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// with a binary search.
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for (DwarfRegNumsMapTy::iterator
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I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
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int RegNo = I->second[i];
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if (RegNo == -1) // -1 is the default value, don't emit a mapping.
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continue;
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OS << " { " << getQualifiedName(I->first) << ", " << RegNo
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<< "U },\n";
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}
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OS << "};\n";
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} else {
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OS << ";\n";
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}
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// We have to store the size in a const global, it's used in multiple
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// places.
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OS << "extern const unsigned " << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
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if (!isCtor)
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OS << " = sizeof(" << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
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<< "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
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else
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OS << ";\n\n";
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}
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}
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}
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void
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RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
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const std::vector<CodeGenRegister*> &Regs,
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bool isCtor) {
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// Emit the initializer so the tables from EmitRegMappingTables get wired up
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// to the MCRegisterInfo object.
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unsigned maxLength = 0;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *Reg = Regs[i]->TheDef;
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maxLength = std::max((size_t)maxLength,
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Reg->getValueAsListOfInts("DwarfNumbers").size());
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}
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if (!maxLength)
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return;
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std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
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// Emit reverse information about the dwarf register numbers.
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for (unsigned j = 0; j < 2; ++j) {
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OS << " switch (";
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if (j == 0)
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OS << "DwarfFlavour";
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else
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OS << "EHFlavour";
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OS << ") {\n"
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<< " default:\n"
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<< " llvm_unreachable(\"Unknown DWARF flavour\");\n";
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for (unsigned i = 0, e = maxLength; i != e; ++i) {
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OS << " case " << i << ":\n";
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OS << " ";
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if (!isCtor)
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OS << "RI->";
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std::string Tmp;
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raw_string_ostream(Tmp) << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
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<< "Dwarf2L";
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OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
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if (j == 0)
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OS << "false";
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else
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OS << "true";
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OS << ");\n";
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OS << " break;\n";
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}
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OS << " }\n";
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}
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// Emit information about the dwarf register numbers.
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for (unsigned j = 0; j < 2; ++j) {
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OS << " switch (";
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if (j == 0)
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OS << "DwarfFlavour";
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else
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OS << "EHFlavour";
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OS << ") {\n"
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<< " default:\n"
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<< " llvm_unreachable(\"Unknown DWARF flavour\");\n";
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for (unsigned i = 0, e = maxLength; i != e; ++i) {
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OS << " case " << i << ":\n";
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OS << " ";
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if (!isCtor)
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OS << "RI->";
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std::string Tmp;
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raw_string_ostream(Tmp) << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
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<< "L2Dwarf";
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OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
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if (j == 0)
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OS << "false";
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else
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OS << "true";
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OS << ");\n";
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OS << " break;\n";
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}
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OS << " }\n";
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}
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}
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// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
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// Width is the number of bits per hex number.
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static void printBitVectorAsHex(raw_ostream &OS,
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const BitVector &Bits,
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unsigned Width) {
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assert(Width <= 32 && "Width too large");
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unsigned Digits = (Width + 3) / 4;
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for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
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unsigned Value = 0;
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for (unsigned j = 0; j != Width && i + j != e; ++j)
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Value |= Bits.test(i + j) << j;
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OS << format("0x%0*x, ", Digits, Value);
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}
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}
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// Helper to emit a set of bits into a constant byte array.
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class BitVectorEmitter {
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BitVector Values;
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public:
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void add(unsigned v) {
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if (v >= Values.size())
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Values.resize(((v/8)+1)*8); // Round up to the next byte.
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Values[v] = true;
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}
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void print(raw_ostream &OS) {
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printBitVectorAsHex(OS, Values, 8);
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}
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};
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static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
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OS << getQualifiedName(Reg->TheDef);
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}
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static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
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OS << getEnumName(VT);
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}
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|
|
static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
|
|
OS << Idx->getQualifiedName();
|
|
}
|
|
|
|
//
|
|
// runMCDesc - Print out MC register descriptions.
|
|
//
|
|
void
|
|
RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|
CodeGenRegBank &RegBank) {
|
|
EmitSourceFileHeader("MC Register Information", OS);
|
|
|
|
OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
|
|
OS << "#undef GET_REGINFO_MC_DESC\n";
|
|
|
|
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
|
|
std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
|
|
RegBank.computeOverlaps(Overlaps);
|
|
|
|
// The lists of sub-registers, super-registers, and overlaps all go in the
|
|
// same array. That allows us to share suffixes.
|
|
typedef std::vector<const CodeGenRegister*> RegVec;
|
|
SmallVector<RegVec, 4> SubRegLists(Regs.size());
|
|
SmallVector<RegVec, 4> OverlapLists(Regs.size());
|
|
SequenceToOffsetTable<RegVec, CodeGenRegister::Less> RegSeqs;
|
|
|
|
// Precompute register lists for the SequenceToOffsetTable.
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
const CodeGenRegister *Reg = Regs[i];
|
|
|
|
// Compute the ordered sub-register list.
|
|
SetVector<const CodeGenRegister*> SR;
|
|
Reg->addSubRegsPreOrder(SR, RegBank);
|
|
RegVec &SubRegList = SubRegLists[i];
|
|
SubRegList.assign(SR.begin(), SR.end());
|
|
RegSeqs.add(SubRegList);
|
|
|
|
// Super-registers are already computed.
|
|
const RegVec &SuperRegList = Reg->getSuperRegs();
|
|
RegSeqs.add(SuperRegList);
|
|
|
|
// The list of overlaps doesn't need to have any particular order, except
|
|
// Reg itself must be the first element. Pick an ordering that has one of
|
|
// the other lists as a suffix.
|
|
RegVec &OverlapList = OverlapLists[i];
|
|
const RegVec &Suffix = SubRegList.size() > SuperRegList.size() ?
|
|
SubRegList : SuperRegList;
|
|
CodeGenRegister::Set Omit(Suffix.begin(), Suffix.end());
|
|
|
|
// First element is Reg itself.
|
|
OverlapList.push_back(Reg);
|
|
Omit.insert(Reg);
|
|
|
|
// Any elements not in Suffix.
|
|
const CodeGenRegister::Set &OSet = Overlaps[Reg];
|
|
std::set_difference(OSet.begin(), OSet.end(),
|
|
Omit.begin(), Omit.end(),
|
|
std::back_inserter(OverlapList),
|
|
CodeGenRegister::Less());
|
|
|
|
// Finally, Suffix itself.
|
|
OverlapList.insert(OverlapList.end(), Suffix.begin(), Suffix.end());
|
|
RegSeqs.add(OverlapList);
|
|
}
|
|
|
|
// Compute the final layout of the sequence table.
|
|
RegSeqs.layout();
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
const std::string &TargetName = Target.getName();
|
|
|
|
// Emit the shared table of register lists.
|
|
OS << "extern const uint16_t " << TargetName << "RegLists[] = {\n";
|
|
RegSeqs.emit(OS, printRegister);
|
|
OS << "};\n\n";
|
|
|
|
OS << "extern const MCRegisterDesc " << TargetName
|
|
<< "RegDesc[] = { // Descriptors\n";
|
|
OS << " { \"NOREG\", 0, 0, 0 },\n";
|
|
|
|
// Emit the register descriptors now.
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
const CodeGenRegister *Reg = Regs[i];
|
|
OS << " { \"" << Reg->getName() << "\", "
|
|
<< RegSeqs.get(OverlapLists[i]) << ", "
|
|
<< RegSeqs.get(SubRegLists[i]) << ", "
|
|
<< RegSeqs.get(Reg->getSuperRegs()) << " },\n";
|
|
}
|
|
OS << "};\n\n"; // End of register descriptors...
|
|
|
|
ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
|
|
|
|
// Loop over all of the register classes... emitting each one.
|
|
OS << "namespace { // Register classes...\n";
|
|
|
|
// Emit the register enum value arrays for each RegisterClass
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
ArrayRef<Record*> Order = RC.getOrder();
|
|
|
|
// Give the register class a legal C name if it's anonymous.
|
|
std::string Name = RC.getName();
|
|
|
|
// Emit the register list now.
|
|
OS << " // " << Name << " Register Class...\n"
|
|
<< " const uint16_t " << Name
|
|
<< "[] = {\n ";
|
|
for (unsigned i = 0, e = Order.size(); i != e; ++i) {
|
|
Record *Reg = Order[i];
|
|
OS << getQualifiedName(Reg) << ", ";
|
|
}
|
|
OS << "\n };\n\n";
|
|
|
|
OS << " // " << Name << " Bit set.\n"
|
|
<< " const uint8_t " << Name
|
|
<< "Bits[] = {\n ";
|
|
BitVectorEmitter BVE;
|
|
for (unsigned i = 0, e = Order.size(); i != e; ++i) {
|
|
Record *Reg = Order[i];
|
|
BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
|
|
}
|
|
BVE.print(OS);
|
|
OS << "\n };\n\n";
|
|
|
|
}
|
|
OS << "}\n\n";
|
|
|
|
OS << "extern const MCRegisterClass " << TargetName
|
|
<< "MCRegisterClasses[] = {\n";
|
|
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
|
|
// Asserts to make sure values will fit in table assuming types from
|
|
// MCRegisterInfo.h
|
|
assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
|
|
assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
|
|
assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
|
|
|
|
OS << " { " << '\"' << RC.getName() << "\", "
|
|
<< RC.getName() << ", " << RC.getName() << "Bits, "
|
|
<< RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
|
|
<< RC.getQualifiedName() + "RegClassID" << ", "
|
|
<< RC.SpillSize/8 << ", "
|
|
<< RC.SpillAlignment/8 << ", "
|
|
<< RC.CopyCost << ", "
|
|
<< RC.Allocatable << " },\n";
|
|
}
|
|
|
|
OS << "};\n\n";
|
|
|
|
// Emit the data table for getSubReg().
|
|
ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
|
|
if (SubRegIndices.size()) {
|
|
OS << "const uint16_t " << TargetName << "SubRegTable[]["
|
|
<< SubRegIndices.size() << "] = {\n";
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
|
|
OS << " /* " << Regs[i]->TheDef->getName() << " */\n";
|
|
if (SRM.empty()) {
|
|
OS << " {0},\n";
|
|
continue;
|
|
}
|
|
OS << " {";
|
|
for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
|
|
// FIXME: We really should keep this to 80 columns...
|
|
CodeGenRegister::SubRegMap::const_iterator SubReg =
|
|
SRM.find(SubRegIndices[j]);
|
|
if (SubReg != SRM.end())
|
|
OS << getQualifiedName(SubReg->second->TheDef);
|
|
else
|
|
OS << "0";
|
|
if (j != je - 1)
|
|
OS << ", ";
|
|
}
|
|
OS << "}" << (i != e ? "," : "") << "\n";
|
|
}
|
|
OS << "};\n\n";
|
|
OS << "const uint16_t *get" << TargetName
|
|
<< "SubRegTable() {\n return (const uint16_t *)" << TargetName
|
|
<< "SubRegTable;\n}\n\n";
|
|
}
|
|
|
|
EmitRegMappingTables(OS, Regs, false);
|
|
|
|
// MCRegisterInfo initialization routine.
|
|
OS << "static inline void Init" << TargetName
|
|
<< "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
|
|
<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
|
|
OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
|
|
<< Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
|
|
<< RegisterClasses.size() << ", " << TargetName << "RegLists, ";
|
|
if (SubRegIndices.size() != 0)
|
|
OS << "(uint16_t*)" << TargetName << "SubRegTable, "
|
|
<< SubRegIndices.size() << ");\n\n";
|
|
else
|
|
OS << "NULL, 0);\n\n";
|
|
|
|
EmitRegMapping(OS, Regs, false);
|
|
|
|
OS << "}\n\n";
|
|
|
|
OS << "} // End llvm namespace \n";
|
|
OS << "#endif // GET_REGINFO_MC_DESC\n\n";
|
|
}
|
|
|
|
void
|
|
RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
|
|
CodeGenRegBank &RegBank) {
|
|
EmitSourceFileHeader("Register Information Header Fragment", OS);
|
|
|
|
OS << "\n#ifdef GET_REGINFO_HEADER\n";
|
|
OS << "#undef GET_REGINFO_HEADER\n";
|
|
|
|
const std::string &TargetName = Target.getName();
|
|
std::string ClassName = TargetName + "GenRegisterInfo";
|
|
|
|
OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
|
|
<< " explicit " << ClassName
|
|
<< "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
|
|
<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
|
|
<< " { return false; }\n";
|
|
if (!RegBank.getSubRegIndices().empty()) {
|
|
OS << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
|
|
<< " const TargetRegisterClass *"
|
|
"getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n";
|
|
}
|
|
OS << " const RegClassWeight &getRegClassWeight("
|
|
<< "const TargetRegisterClass *RC) const;\n"
|
|
<< " unsigned getNumRegPressureSets() const;\n"
|
|
<< " const char *getRegPressureSetName(unsigned Idx) const;\n"
|
|
<< " unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
|
|
<< " const int *getRegClassPressureSets("
|
|
<< "const TargetRegisterClass *RC) const;\n"
|
|
<< "};\n\n";
|
|
|
|
ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
|
|
|
|
if (!RegisterClasses.empty()) {
|
|
OS << "namespace " << RegisterClasses[0]->Namespace
|
|
<< " { // Register classes\n";
|
|
|
|
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[i];
|
|
const std::string &Name = RC.getName();
|
|
|
|
// Output the extern for the instance.
|
|
OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
|
|
}
|
|
OS << "} // end of namespace " << TargetName << "\n\n";
|
|
}
|
|
OS << "} // End llvm namespace \n";
|
|
OS << "#endif // GET_REGINFO_HEADER\n\n";
|
|
}
|
|
|
|
//
|
|
// runTargetDesc - Output the target register and register file descriptions.
|
|
//
|
|
void
|
|
RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|
CodeGenRegBank &RegBank){
|
|
EmitSourceFileHeader("Target Register and Register Classes Information", OS);
|
|
|
|
OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
|
|
OS << "#undef GET_REGINFO_TARGET_DESC\n";
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
// Get access to MCRegisterClass data.
|
|
OS << "extern const MCRegisterClass " << Target.getName()
|
|
<< "MCRegisterClasses[];\n";
|
|
|
|
// Start out by emitting each of the register classes.
|
|
ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
|
|
ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
|
|
|
|
// Collect all registers belonging to any allocatable class.
|
|
std::set<Record*> AllocatableRegs;
|
|
|
|
// Collect allocatable registers.
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
ArrayRef<Record*> Order = RC.getOrder();
|
|
|
|
if (RC.Allocatable)
|
|
AllocatableRegs.insert(Order.begin(), Order.end());
|
|
}
|
|
|
|
// Build a shared array of value types.
|
|
SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
|
|
VTSeqs.add(RegisterClasses[rc]->VTs);
|
|
VTSeqs.layout();
|
|
OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
|
|
VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
|
|
OS << "};\n";
|
|
|
|
// Emit SubRegIndex names, skipping 0
|
|
OS << "\nstatic const char *const SubRegIndexTable[] = { \"";
|
|
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
|
|
OS << SubRegIndices[i]->getName();
|
|
if (i+1 != e)
|
|
OS << "\", \"";
|
|
}
|
|
OS << "\" };\n\n";
|
|
|
|
// Emit names of the anonymous subreg indices.
|
|
unsigned NamedIndices = RegBank.getNumNamedIndices();
|
|
if (SubRegIndices.size() > NamedIndices) {
|
|
OS << " enum {";
|
|
for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
|
|
OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
|
|
if (i+1 != e)
|
|
OS << ',';
|
|
}
|
|
OS << "\n };\n\n";
|
|
}
|
|
OS << "\n";
|
|
|
|
// Now that all of the structs have been emitted, emit the instances.
|
|
if (!RegisterClasses.empty()) {
|
|
OS << "\nstatic const TargetRegisterClass *const "
|
|
<< "NullRegClasses[] = { NULL };\n\n";
|
|
|
|
// Emit register class bit mask tables. The first bit mask emitted for a
|
|
// register class, RC, is the set of sub-classes, including RC itself.
|
|
//
|
|
// If RC has super-registers, also create a list of subreg indices and bit
|
|
// masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
|
|
// SuperRC, that satisfies:
|
|
//
|
|
// For all SuperReg in SuperRC: SuperReg:Idx in RC
|
|
//
|
|
// The 0-terminated list of subreg indices starts at:
|
|
//
|
|
// RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
|
|
//
|
|
// The corresponding bitmasks follow the sub-class mask in memory. Each
|
|
// mask has RCMaskWords uint32_t entries.
|
|
//
|
|
// Every bit mask present in the list has at least one bit set.
|
|
|
|
// Compress the sub-reg index lists.
|
|
typedef std::vector<const CodeGenSubRegIndex*> IdxList;
|
|
SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
|
|
SequenceToOffsetTable<IdxList> SuperRegIdxSeqs;
|
|
BitVector MaskBV(RegisterClasses.size());
|
|
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
|
|
printBitVectorAsHex(OS, RC.getSubClasses(), 32);
|
|
|
|
// Emit super-reg class masks for any relevant SubRegIndices that can
|
|
// project into RC.
|
|
IdxList &SRIList = SuperRegIdxLists[rc];
|
|
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
|
|
CodeGenSubRegIndex *Idx = SubRegIndices[sri];
|
|
MaskBV.reset();
|
|
RC.getSuperRegClasses(Idx, MaskBV);
|
|
if (MaskBV.none())
|
|
continue;
|
|
SRIList.push_back(Idx);
|
|
OS << "\n ";
|
|
printBitVectorAsHex(OS, MaskBV, 32);
|
|
OS << "// " << Idx->getName();
|
|
}
|
|
SuperRegIdxSeqs.add(SRIList);
|
|
OS << "\n};\n\n";
|
|
}
|
|
|
|
OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
|
|
SuperRegIdxSeqs.layout();
|
|
SuperRegIdxSeqs.emit(OS, printSubRegIndex);
|
|
OS << "};\n\n";
|
|
|
|
// Emit NULL terminated super-class lists.
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
|
|
|
|
// Skip classes without supers. We can reuse NullRegClasses.
|
|
if (Supers.empty())
|
|
continue;
|
|
|
|
OS << "static const TargetRegisterClass *const "
|
|
<< RC.getName() << "Superclasses[] = {\n";
|
|
for (unsigned i = 0; i != Supers.size(); ++i)
|
|
OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
|
|
OS << " NULL\n};\n\n";
|
|
}
|
|
|
|
// Emit methods.
|
|
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[i];
|
|
if (!RC.AltOrderSelect.empty()) {
|
|
OS << "\nstatic inline unsigned " << RC.getName()
|
|
<< "AltOrderSelect(const MachineFunction &MF) {"
|
|
<< RC.AltOrderSelect << "}\n\n"
|
|
<< "static ArrayRef<uint16_t> " << RC.getName()
|
|
<< "GetRawAllocationOrder(const MachineFunction &MF) {\n";
|
|
for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
|
|
ArrayRef<Record*> Elems = RC.getOrder(oi);
|
|
if (!Elems.empty()) {
|
|
OS << " static const uint16_t AltOrder" << oi << "[] = {";
|
|
for (unsigned elem = 0; elem != Elems.size(); ++elem)
|
|
OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
|
|
OS << " };\n";
|
|
}
|
|
}
|
|
OS << " const MCRegisterClass &MCR = " << Target.getName()
|
|
<< "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
|
|
<< " const ArrayRef<uint16_t> Order[] = {\n"
|
|
<< " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
|
|
for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
|
|
if (RC.getOrder(oi).empty())
|
|
OS << "),\n ArrayRef<uint16_t>(";
|
|
else
|
|
OS << "),\n makeArrayRef(AltOrder" << oi;
|
|
OS << ")\n };\n const unsigned Select = " << RC.getName()
|
|
<< "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
|
|
<< ");\n return Order[Select];\n}\n";
|
|
}
|
|
}
|
|
|
|
// Now emit the actual value-initialized register class instances.
|
|
OS << "namespace " << RegisterClasses[0]->Namespace
|
|
<< " { // Register class instances\n";
|
|
|
|
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[i];
|
|
OS << " extern const TargetRegisterClass "
|
|
<< RegisterClasses[i]->getName() << "RegClass = {\n "
|
|
<< '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
|
|
<< "RegClassID],\n "
|
|
<< "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
|
|
<< RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + "
|
|
<< SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n ";
|
|
if (RC.getSuperClasses().empty())
|
|
OS << "NullRegClasses,\n ";
|
|
else
|
|
OS << RC.getName() << "Superclasses,\n ";
|
|
if (RC.AltOrderSelect.empty())
|
|
OS << "0\n";
|
|
else
|
|
OS << RC.getName() << "GetRawAllocationOrder\n";
|
|
OS << " };\n\n";
|
|
}
|
|
|
|
OS << "}\n";
|
|
}
|
|
|
|
OS << "\nnamespace {\n";
|
|
OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
|
|
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
|
|
OS << " &" << RegisterClasses[i]->getQualifiedName()
|
|
<< "RegClass,\n";
|
|
OS << " };\n";
|
|
OS << "}\n"; // End of anonymous namespace...
|
|
|
|
// Emit extra information about registers.
|
|
const std::string &TargetName = Target.getName();
|
|
OS << "\nstatic const TargetRegisterInfoDesc "
|
|
<< TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
|
|
OS << " { 0, 0 },\n";
|
|
|
|
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
const CodeGenRegister &Reg = *Regs[i];
|
|
OS << " { ";
|
|
OS << Reg.CostPerUse << ", "
|
|
<< int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
|
|
}
|
|
OS << "};\n"; // End of register descriptors...
|
|
|
|
|
|
std::string ClassName = Target.getName() + "GenRegisterInfo";
|
|
|
|
// Emit composeSubRegIndices
|
|
if (!SubRegIndices.empty()) {
|
|
OS << "unsigned " << ClassName
|
|
<< "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
|
|
<< " switch (IdxA) {\n"
|
|
<< " default:\n return IdxB;\n";
|
|
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
|
|
bool Open = false;
|
|
for (unsigned j = 0; j != e; ++j) {
|
|
if (CodeGenSubRegIndex *Comp =
|
|
SubRegIndices[i]->compose(SubRegIndices[j])) {
|
|
if (!Open) {
|
|
OS << " case " << SubRegIndices[i]->getQualifiedName()
|
|
<< ": switch(IdxB) {\n default: return IdxB;\n";
|
|
Open = true;
|
|
}
|
|
OS << " case " << SubRegIndices[j]->getQualifiedName()
|
|
<< ": return " << Comp->getQualifiedName() << ";\n";
|
|
}
|
|
}
|
|
if (Open)
|
|
OS << " }\n";
|
|
}
|
|
OS << " }\n}\n\n";
|
|
}
|
|
|
|
// Emit getSubClassWithSubReg.
|
|
if (!SubRegIndices.empty()) {
|
|
OS << "const TargetRegisterClass *" << ClassName
|
|
<< "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
|
|
<< " const {\n";
|
|
// Use the smallest type that can hold a regclass ID with room for a
|
|
// sentinel.
|
|
if (RegisterClasses.size() < UINT8_MAX)
|
|
OS << " static const uint8_t Table[";
|
|
else if (RegisterClasses.size() < UINT16_MAX)
|
|
OS << " static const uint16_t Table[";
|
|
else
|
|
throw "Too many register classes.";
|
|
OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
|
|
for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rci];
|
|
OS << " {\t// " << RC.getName() << "\n";
|
|
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
|
|
CodeGenSubRegIndex *Idx = SubRegIndices[sri];
|
|
if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
|
|
OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
|
|
<< " -> " << SRC->getName() << "\n";
|
|
else
|
|
OS << " 0,\t// " << Idx->getName() << "\n";
|
|
}
|
|
OS << " },\n";
|
|
}
|
|
OS << " };\n assert(RC && \"Missing regclass\");\n"
|
|
<< " if (!Idx) return RC;\n --Idx;\n"
|
|
<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
|
|
<< " unsigned TV = Table[RC->getID()][Idx];\n"
|
|
<< " return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
|
|
}
|
|
|
|
EmitRegUnitPressure(OS, RegBank, ClassName);
|
|
|
|
// Emit the constructor of the class...
|
|
OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
|
|
OS << "extern const uint16_t " << TargetName << "RegLists[];\n";
|
|
if (SubRegIndices.size() != 0)
|
|
OS << "extern const uint16_t *get" << TargetName
|
|
<< "SubRegTable();\n";
|
|
|
|
EmitRegMappingTables(OS, Regs, true);
|
|
|
|
OS << ClassName << "::\n" << ClassName
|
|
<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
|
|
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
|
|
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
|
|
<< " SubRegIndexTable) {\n"
|
|
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
|
|
<< Regs.size()+1 << ", RA,\n " << TargetName
|
|
<< "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
|
|
<< " " << TargetName << "RegLists,\n"
|
|
<< " ";
|
|
if (SubRegIndices.size() != 0)
|
|
OS << "get" << TargetName << "SubRegTable(), "
|
|
<< SubRegIndices.size() << ");\n\n";
|
|
else
|
|
OS << "NULL, 0);\n\n";
|
|
|
|
EmitRegMapping(OS, Regs, true);
|
|
|
|
OS << "}\n\n";
|
|
|
|
|
|
// Emit CalleeSavedRegs information.
|
|
std::vector<Record*> CSRSets =
|
|
Records.getAllDerivedDefinitions("CalleeSavedRegs");
|
|
for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
|
|
Record *CSRSet = CSRSets[i];
|
|
const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
|
|
assert(Regs && "Cannot expand CalleeSavedRegs instance");
|
|
|
|
// Emit the *_SaveList list of callee-saved registers.
|
|
OS << "static const uint16_t " << CSRSet->getName()
|
|
<< "_SaveList[] = { ";
|
|
for (unsigned r = 0, re = Regs->size(); r != re; ++r)
|
|
OS << getQualifiedName((*Regs)[r]) << ", ";
|
|
OS << "0 };\n";
|
|
|
|
// Emit the *_RegMask bit mask of call-preserved registers.
|
|
OS << "static const uint32_t " << CSRSet->getName()
|
|
<< "_RegMask[] = { ";
|
|
printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
|
|
OS << "};\n";
|
|
}
|
|
OS << "\n\n";
|
|
|
|
OS << "} // End llvm namespace \n";
|
|
OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
|
|
}
|
|
|
|
void RegisterInfoEmitter::run(raw_ostream &OS) {
|
|
CodeGenTarget Target(Records);
|
|
CodeGenRegBank &RegBank = Target.getRegBank();
|
|
RegBank.computeDerivedInfo();
|
|
|
|
runEnums(OS, Target, RegBank);
|
|
runMCDesc(OS, Target, RegBank);
|
|
runTargetHeader(OS, Target, RegBank);
|
|
runTargetDesc(OS, Target, RegBank);
|
|
}
|