mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.4 KiB
LLVM
57 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=ptx32 -mattr=+ptx20 | FileCheck %s
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define ptx_device float @test_sqrt_f32(float %x) {
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entry:
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; CHECK: sqrt.rn.f32 r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: ret;
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%y = call float @llvm.sqrt.f32(float %x)
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ret float %y
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}
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define ptx_device double @test_sqrt_f64(double %x) {
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entry:
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; CHECK: sqrt.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}};
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; CHECK-NEXT: ret;
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%y = call double @llvm.sqrt.f64(double %x)
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ret double %y
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}
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define ptx_device float @test_sin_f32(float %x) {
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entry:
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; CHECK: sin.approx.f32 r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: ret;
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%y = call float @llvm.sin.f32(float %x)
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ret float %y
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}
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define ptx_device double @test_sin_f64(double %x) {
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entry:
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; CHECK: sin.approx.f64 rd{{[0-9]+}}, rd{{[0-9]+}};
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; CHECK-NEXT: ret;
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%y = call double @llvm.sin.f64(double %x)
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ret double %y
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}
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define ptx_device float @test_cos_f32(float %x) {
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entry:
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; CHECK: cos.approx.f32 r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: ret;
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%y = call float @llvm.cos.f32(float %x)
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ret float %y
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}
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define ptx_device double @test_cos_f64(double %x) {
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entry:
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; CHECK: cos.approx.f64 rd{{[0-9]+}}, rd{{[0-9]+}};
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; CHECK-NEXT: ret;
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%y = call double @llvm.cos.f64(double %x)
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ret double %y
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}
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declare float @llvm.sqrt.f32(float)
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declare double @llvm.sqrt.f64(double)
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declare float @llvm.sin.f32(float)
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declare double @llvm.sin.f64(double)
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declare float @llvm.cos.f32(float)
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declare double @llvm.cos.f64(double)
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