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685c350ae7
(yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
3.4 KiB
C++
98 lines
3.4 KiB
C++
//===-- ARM/ARMFixupKinds.h - ARM Specific Fixup Entries --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_ARM_ARMFIXUPKINDS_H
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#define LLVM_ARM_ARMFIXUPKINDS_H
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#include "llvm/MC/MCFixup.h"
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namespace llvm {
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namespace ARM {
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enum Fixups {
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// fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
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// addresses
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fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
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// fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
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// the 16-bit halfwords reordered.
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fixup_t2_ldst_pcrel_12,
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// fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
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// used in VFP instructions where the lower 2 bits are not encoded
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// (so it's encoded as an 8-bit immediate).
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fixup_arm_pcrel_10,
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// fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
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// the short-swapped encoding of Thumb2 instructions.
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fixup_t2_pcrel_10,
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// fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
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// addresses where the lower 2 bits are not encoded (so it's encoded as an
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// 8-bit immediate).
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fixup_thumb_adr_pcrel_10,
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// fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
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// instruction.
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fixup_arm_adr_pcrel_12,
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// fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
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// instruction.
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fixup_t2_adr_pcrel_12,
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// fixup_arm_condbranch - 24-bit PC relative relocation for conditional branch
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// instructions.
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fixup_arm_condbranch,
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// fixup_arm_uncondbranch - 24-bit PC relative relocation for
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// branch instructions. (unconditional)
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fixup_arm_uncondbranch,
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// fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct
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// uconditional branch instructions.
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fixup_t2_condbranch,
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// fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct
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// branch unconditional branch instructions.
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fixup_t2_uncondbranch,
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// fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
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fixup_arm_thumb_br,
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// fixup_arm_thumb_blx - Fixup for Thumb BL instructions.
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fixup_arm_thumb_bl,
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// fixup_arm_thumb_blx - Fixup for Thumb BLX instructions.
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fixup_arm_thumb_blx,
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// fixup_arm_thumb_cb - Fixup for Thumb branch instructions.
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fixup_arm_thumb_cb,
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// fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
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fixup_arm_thumb_cp,
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// fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
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fixup_arm_thumb_bcc,
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// The next two are for the movt/movw pair
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// the 16bit imm field are split into imm{15-12} and imm{11-0}
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fixup_arm_movt_hi16, // :upper16:
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fixup_arm_movw_lo16, // :lower16:
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fixup_t2_movt_hi16, // :upper16:
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fixup_t2_movw_lo16, // :lower16:
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// It is possible to create an "immediate" that happens to be pcrel.
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// movw r0, :lower16:Foo-(Bar+8) and movt r0, :upper16:Foo-(Bar+8)
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// result in different reloc tags than the above two.
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// Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC
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fixup_arm_movt_hi16_pcrel, // :upper16:
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fixup_arm_movw_lo16_pcrel, // :lower16:
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fixup_t2_movt_hi16_pcrel, // :upper16:
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fixup_t2_movw_lo16_pcrel, // :lower16:
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// Marker
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LastTargetFixupKind,
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NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
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};
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}
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}
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#endif
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