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https://github.com/c64scene-ar/llvm-6502.git
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c499ecd1d1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206887 91177308-0d34-0410-b5e6-96231b3b80d8
244 lines
9.2 KiB
LLVM
244 lines
9.2 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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; Intrinsic wrangling and arm64 does it differently.
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declare <1 x i8> @llvm.arm.neon.vqaddu.v1i8(<1 x i8>, <1 x i8>)
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declare <1 x i8> @llvm.arm.neon.vqadds.v1i8(<1 x i8>, <1 x i8>)
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define <1 x i8> @test_uqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
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; CHECK: test_uqadd_v1i8_aarch64:
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%tmp1 = call <1 x i8> @llvm.arm.neon.vqaddu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
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;CHECK: uqadd {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
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ret <1 x i8> %tmp1
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}
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define <1 x i8> @test_sqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
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; CHECK: test_sqadd_v1i8_aarch64:
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%tmp1 = call <1 x i8> @llvm.arm.neon.vqadds.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
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;CHECK: sqadd {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
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ret <1 x i8> %tmp1
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}
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declare <1 x i8> @llvm.arm.neon.vqsubu.v1i8(<1 x i8>, <1 x i8>)
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declare <1 x i8> @llvm.arm.neon.vqsubs.v1i8(<1 x i8>, <1 x i8>)
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define <1 x i8> @test_uqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
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; CHECK: test_uqsub_v1i8_aarch64:
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%tmp1 = call <1 x i8> @llvm.arm.neon.vqsubu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
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;CHECK: uqsub {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
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ret <1 x i8> %tmp1
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}
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define <1 x i8> @test_sqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
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; CHECK: test_sqsub_v1i8_aarch64:
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%tmp1 = call <1 x i8> @llvm.arm.neon.vqsubs.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
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;CHECK: sqsub {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
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ret <1 x i8> %tmp1
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}
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declare <1 x i16> @llvm.arm.neon.vqaddu.v1i16(<1 x i16>, <1 x i16>)
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declare <1 x i16> @llvm.arm.neon.vqadds.v1i16(<1 x i16>, <1 x i16>)
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define <1 x i16> @test_uqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
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; CHECK: test_uqadd_v1i16_aarch64:
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%tmp1 = call <1 x i16> @llvm.arm.neon.vqaddu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
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;CHECK: uqadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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ret <1 x i16> %tmp1
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}
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define <1 x i16> @test_sqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
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; CHECK: test_sqadd_v1i16_aarch64:
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%tmp1 = call <1 x i16> @llvm.arm.neon.vqadds.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
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;CHECK: sqadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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ret <1 x i16> %tmp1
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}
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declare <1 x i16> @llvm.arm.neon.vqsubu.v1i16(<1 x i16>, <1 x i16>)
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declare <1 x i16> @llvm.arm.neon.vqsubs.v1i16(<1 x i16>, <1 x i16>)
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define <1 x i16> @test_uqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
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; CHECK: test_uqsub_v1i16_aarch64:
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%tmp1 = call <1 x i16> @llvm.arm.neon.vqsubu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
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;CHECK: uqsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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ret <1 x i16> %tmp1
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}
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define <1 x i16> @test_sqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
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; CHECK: test_sqsub_v1i16_aarch64:
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%tmp1 = call <1 x i16> @llvm.arm.neon.vqsubs.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
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;CHECK: sqsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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ret <1 x i16> %tmp1
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}
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declare <1 x i32> @llvm.arm.neon.vqaddu.v1i32(<1 x i32>, <1 x i32>)
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declare <1 x i32> @llvm.arm.neon.vqadds.v1i32(<1 x i32>, <1 x i32>)
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define <1 x i32> @test_uqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
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; CHECK: test_uqadd_v1i32_aarch64:
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%tmp1 = call <1 x i32> @llvm.arm.neon.vqaddu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
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;CHECK: uqadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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ret <1 x i32> %tmp1
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}
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define <1 x i32> @test_sqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
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; CHECK: test_sqadd_v1i32_aarch64:
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%tmp1 = call <1 x i32> @llvm.arm.neon.vqadds.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
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;CHECK: sqadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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ret <1 x i32> %tmp1
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}
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declare <1 x i32> @llvm.arm.neon.vqsubu.v1i32(<1 x i32>, <1 x i32>)
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declare <1 x i32> @llvm.arm.neon.vqsubs.v1i32(<1 x i32>, <1 x i32>)
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define <1 x i32> @test_uqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
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; CHECK: test_uqsub_v1i32_aarch64:
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%tmp1 = call <1 x i32> @llvm.arm.neon.vqsubu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
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;CHECK: uqsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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ret <1 x i32> %tmp1
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}
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define <1 x i32> @test_sqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
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; CHECK: test_sqsub_v1i32_aarch64:
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%tmp1 = call <1 x i32> @llvm.arm.neon.vqsubs.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
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;CHECK: sqsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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ret <1 x i32> %tmp1
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}
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declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>)
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define <1 x i64> @test_uqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
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; CHECK: test_uqadd_v1i64_aarch64:
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%tmp1 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
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;CHECK: uqadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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ret <1 x i64> %tmp1
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}
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define <1 x i64> @test_sqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
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; CHECK: test_sqadd_v1i64_aarch64:
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%tmp1 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
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;CHECK: sqadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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ret <1 x i64> %tmp1
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}
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declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>)
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define <1 x i64> @test_uqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
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; CHECK: test_uqsub_v1i64_aarch64:
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%tmp1 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
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;CHECK: uqsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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ret <1 x i64> %tmp1
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}
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define <1 x i64> @test_sqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
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; CHECK: test_sqsub_v1i64_aarch64:
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%tmp1 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
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;CHECK: sqsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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ret <1 x i64> %tmp1
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}
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define i8 @test_vuqaddb_s8(i8 %a, i8 %b) {
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; CHECK: test_vuqaddb_s8
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; CHECK: suqadd {{b[0-9]+}}, {{b[0-9]+}}
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entry:
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%vuqadd.i = insertelement <1 x i8> undef, i8 %a, i32 0
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%vuqadd1.i = insertelement <1 x i8> undef, i8 %b, i32 0
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%vuqadd2.i = call <1 x i8> @llvm.aarch64.neon.vuqadd.v1i8(<1 x i8> %vuqadd.i, <1 x i8> %vuqadd1.i)
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%0 = extractelement <1 x i8> %vuqadd2.i, i32 0
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ret i8 %0
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}
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declare <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8>, <1 x i8>)
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define i16 @test_vuqaddh_s16(i16 %a, i16 %b) {
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; CHECK: test_vuqaddh_s16
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; CHECK: suqadd {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%vuqadd.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vuqadd1.i = insertelement <1 x i16> undef, i16 %b, i32 0
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%vuqadd2.i = call <1 x i16> @llvm.aarch64.neon.vuqadd.v1i16(<1 x i16> %vuqadd.i, <1 x i16> %vuqadd1.i)
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%0 = extractelement <1 x i16> %vuqadd2.i, i32 0
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ret i16 %0
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}
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declare <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16>, <1 x i16>)
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define i32 @test_vuqadds_s32(i32 %a, i32 %b) {
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; CHECK: test_vuqadds_s32
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; CHECK: suqadd {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vuqadd.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vuqadd1.i = insertelement <1 x i32> undef, i32 %b, i32 0
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%vuqadd2.i = call <1 x i32> @llvm.aarch64.neon.vuqadd.v1i32(<1 x i32> %vuqadd.i, <1 x i32> %vuqadd1.i)
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%0 = extractelement <1 x i32> %vuqadd2.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vsqadd.v1i32(<1 x i32>, <1 x i32>)
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define i64 @test_vuqaddd_s64(i64 %a, i64 %b) {
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; CHECK: test_vuqaddd_s64
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; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vuqadd.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vuqadd1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vuqadd2.i = call <1 x i64> @llvm.aarch64.neon.vuqadd.v1i64(<1 x i64> %vuqadd.i, <1 x i64> %vuqadd1.i)
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%0 = extractelement <1 x i64> %vuqadd2.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.vsqadd.v1i64(<1 x i64>, <1 x i64>)
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define i8 @test_vsqaddb_u8(i8 %a, i8 %b) {
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; CHECK: test_vsqaddb_u8
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; CHECK: usqadd {{b[0-9]+}}, {{b[0-9]+}}
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entry:
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%vsqadd.i = insertelement <1 x i8> undef, i8 %a, i32 0
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%vsqadd1.i = insertelement <1 x i8> undef, i8 %b, i32 0
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%vsqadd2.i = call <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8> %vsqadd.i, <1 x i8> %vsqadd1.i)
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%0 = extractelement <1 x i8> %vsqadd2.i, i32 0
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ret i8 %0
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}
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declare <1 x i8> @llvm.aarch64.neon.vuqadd.v1i8(<1 x i8>, <1 x i8>)
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define i16 @test_vsqaddh_u16(i16 %a, i16 %b) {
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; CHECK: test_vsqaddh_u16
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; CHECK: usqadd {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%vsqadd.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vsqadd1.i = insertelement <1 x i16> undef, i16 %b, i32 0
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%vsqadd2.i = call <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16> %vsqadd.i, <1 x i16> %vsqadd1.i)
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%0 = extractelement <1 x i16> %vsqadd2.i, i32 0
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ret i16 %0
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}
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declare <1 x i16> @llvm.aarch64.neon.vuqadd.v1i16(<1 x i16>, <1 x i16>)
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define i32 @test_vsqadds_u32(i32 %a, i32 %b) {
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; CHECK: test_vsqadds_u32
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; CHECK: usqadd {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vsqadd.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vsqadd1.i = insertelement <1 x i32> undef, i32 %b, i32 0
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%vsqadd2.i = call <1 x i32> @llvm.aarch64.neon.vsqadd.v1i32(<1 x i32> %vsqadd.i, <1 x i32> %vsqadd1.i)
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%0 = extractelement <1 x i32> %vsqadd2.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vuqadd.v1i32(<1 x i32>, <1 x i32>)
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define i64 @test_vsqaddd_u64(i64 %a, i64 %b) {
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; CHECK: test_vsqaddd_u64
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; CHECK: usqadd {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vsqadd.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vsqadd1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vsqadd2.i = call <1 x i64> @llvm.aarch64.neon.vsqadd.v1i64(<1 x i64> %vsqadd.i, <1 x i64> %vsqadd1.i)
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%0 = extractelement <1 x i64> %vsqadd2.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.vuqadd.v1i64(<1 x i64>, <1 x i64>)
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