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https://github.com/c64scene-ar/llvm-6502.git
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ae43cab6ba
Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
5.7 KiB
LLVM
140 lines
5.7 KiB
LLVM
; RUN: llc -mtriple x86_64-apple-macosx -mcpu=corei7-avx -combiner-stress-load-slicing < %s -o - | FileCheck %s --check-prefix=STRESS
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; RUN: llc -mtriple x86_64-apple-macosx -mcpu=corei7-avx < %s -o - | FileCheck %s --check-prefix=REGULAR
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;
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; <rdar://problem/14477220>
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%class.Complex = type { float, float }
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; Check that independent slices leads to independent loads then the slices leads to
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; different register file.
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;
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; The layout is:
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; LSB 0 1 2 3 | 4 5 6 7 MSB
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; Low High
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; The base address points to 0 and is 8-bytes aligned.
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; Low slice starts at 0 (base) and is 8-bytes aligned.
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; High slice starts at 4 (base + 4-bytes) and is 4-bytes aligned.
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;
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; STRESS-LABEL: t1:
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; Load out[out_start + 8].real, this is base + 8 * 8 + 0.
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; STRESS: vmovss 64([[BASE:[^(]+]]), [[OUT_Real:%xmm[0-9]+]]
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; Add low slice: out[out_start].real, this is base + 0.
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; STRESS-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
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; Load out[out_start + 8].imm, this is base + 8 * 8 + 4.
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; STRESS-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]]
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; Add high slice: out[out_start].imm, this is base + 4.
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; STRESS-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]]
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; Swap Imm and Real.
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; STRESS-NEXT: vinsertps $16, [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]]
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; Put the results back into out[out_start].
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; STRESS-NEXT: vmovq [[RES_Vec]], ([[BASE]])
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;
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; Same for REGULAR, we eliminate register bank copy with each slices.
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; REGULAR-LABEL: t1:
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; Load out[out_start + 8].real, this is base + 8 * 8 + 0.
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; REGULAR: vmovss 64([[BASE:[^)]+]]), [[OUT_Real:%xmm[0-9]+]]
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; Add low slice: out[out_start].real, this is base + 0.
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; REGULAR-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
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; Load out[out_start + 8].imm, this is base + 8 * 8 + 4.
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; REGULAR-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]]
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; Add high slice: out[out_start].imm, this is base + 4.
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; REGULAR-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]]
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; Swap Imm and Real.
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; REGULAR-NEXT: vinsertps $16, [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]]
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; Put the results back into out[out_start].
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; REGULAR-NEXT: vmovq [[RES_Vec]], ([[BASE]])
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define void @t1(%class.Complex* nocapture %out, i64 %out_start) {
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entry:
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%arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
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%tmp = bitcast %class.Complex* %arrayidx to i64*
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%tmp1 = load i64* %tmp, align 8
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%t0.sroa.0.0.extract.trunc = trunc i64 %tmp1 to i32
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%tmp2 = bitcast i32 %t0.sroa.0.0.extract.trunc to float
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%t0.sroa.2.0.extract.shift = lshr i64 %tmp1, 32
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%t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32
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%tmp3 = bitcast i32 %t0.sroa.2.0.extract.trunc to float
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%add = add i64 %out_start, 8
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%arrayidx2 = getelementptr inbounds %class.Complex* %out, i64 %add
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%i.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 0
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%tmp4 = load float* %i.i, align 4
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%add.i = fadd float %tmp4, %tmp2
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%retval.sroa.0.0.vec.insert.i = insertelement <2 x float> undef, float %add.i, i32 0
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%r.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 1
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%tmp5 = load float* %r.i, align 4
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%add5.i = fadd float %tmp5, %tmp3
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%retval.sroa.0.4.vec.insert.i = insertelement <2 x float> %retval.sroa.0.0.vec.insert.i, float %add5.i, i32 1
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%ref.tmp.sroa.0.0.cast = bitcast %class.Complex* %arrayidx to <2 x float>*
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store <2 x float> %retval.sroa.0.4.vec.insert.i, <2 x float>* %ref.tmp.sroa.0.0.cast, align 4
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
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; Function Attrs: nounwind
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declare void @llvm.lifetime.start(i64, i8* nocapture)
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; Function Attrs: nounwind
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declare void @llvm.lifetime.end(i64, i8* nocapture)
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; Check that we do not read outside of the chunk of bits of the original loads.
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;
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; The 64-bits should have been split in one 32-bits and one 16-bits slices.
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; The 16-bits should be zero extended to match the final type.
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;
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; The memory layout is:
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; LSB 0 1 2 3 | 4 5 | 6 7 MSB
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; Low High
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; The base address points to 0 and is 8-bytes aligned.
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; Low slice starts at 0 (base) and is 8-bytes aligned.
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; High slice starts at 6 (base + 6-bytes) and is 2-bytes aligned.
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;
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; STRESS-LABEL: t2:
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; STRESS: movzwl 6([[BASE:[^)]+]]), %eax
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; STRESS-NEXT: addl ([[BASE]]), %eax
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; STRESS-NEXT: ret
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;
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; For the REGULAR heuristic, this is not profitable to slice things that are not
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; next to each other in memory. Here we have a hole with bytes #4-5.
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; REGULAR-LABEL: t2:
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; REGULAR: shrq $48
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define i32 @t2(%class.Complex* nocapture %out, i64 %out_start) {
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%arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
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%bitcast = bitcast %class.Complex* %arrayidx to i64*
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%chunk64 = load i64* %bitcast, align 8
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%slice32_low = trunc i64 %chunk64 to i32
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%shift48 = lshr i64 %chunk64, 48
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%slice32_high = trunc i64 %shift48 to i32
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%res = add i32 %slice32_high, %slice32_low
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ret i32 %res
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}
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; Check that we do not optimize overlapping slices.
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;
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; The 64-bits should NOT have been split in as slices are overlapping.
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; First slice uses bytes numbered 0 to 3.
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; Second slice uses bytes numbered 6 and 7.
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; Third slice uses bytes numbered 4 to 7.
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;
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; STRESS-LABEL: t3:
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; STRESS: shrq $48
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; STRESS: shrq $32
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;
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; REGULAR-LABEL: t3:
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; REGULAR: shrq $48
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; REGULAR: shrq $32
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define i32 @t3(%class.Complex* nocapture %out, i64 %out_start) {
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%arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
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%bitcast = bitcast %class.Complex* %arrayidx to i64*
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%chunk64 = load i64* %bitcast, align 8
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%slice32_low = trunc i64 %chunk64 to i32
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%shift48 = lshr i64 %chunk64, 48
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%slice32_high = trunc i64 %shift48 to i32
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%shift32 = lshr i64 %chunk64, 32
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%slice32_lowhigh = trunc i64 %shift32 to i32
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%tmpres = add i32 %slice32_high, %slice32_low
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%res = add i32 %slice32_lowhigh, %tmpres
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ret i32 %res
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}
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