mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0082717cb5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193247 91177308-0d34-0410-b5e6-96231b3b80d8
475 lines
16 KiB
C++
475 lines
16 KiB
C++
//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MipsMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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//
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#define DEBUG_TYPE "mccodeemitter"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MCTargetDesc/MipsFixupKinds.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#define GET_INSTRMAP_INFO
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#include "MipsGenInstrInfo.inc"
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using namespace llvm;
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namespace {
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class MipsMCCodeEmitter : public MCCodeEmitter {
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MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
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void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
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const MCInstrInfo &MCII;
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MCContext &Ctx;
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const MCSubtargetInfo &STI;
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bool IsLittleEndian;
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bool IsMicroMips;
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public:
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MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_,
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const MCSubtargetInfo &sti, bool IsLittle) :
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MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {
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IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
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}
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~MipsMCCodeEmitter() {}
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void EmitByte(unsigned char C, raw_ostream &OS) const {
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OS << (char)C;
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}
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void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
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// Output the instruction encoding in little endian byte order.
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// Little-endian byte ordering:
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// mips32r2: 4 | 3 | 2 | 1
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// microMIPS: 2 | 1 | 4 | 3
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if (IsLittleEndian && Size == 4 && IsMicroMips) {
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EmitInstruction(Val>>16, 2, OS);
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EmitInstruction(Val, 2, OS);
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} else {
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for (unsigned i = 0; i < Size; ++i) {
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unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
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EmitByte((Val >> Shift) & 0xff, OS);
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}
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}
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}
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBranchJumpOpValue - Return binary encoding of the jump
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// target operand. If the machine operand requires relocation,
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// record the relocation and return zero.
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unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBranchTargetOpValue - Return binary encoding of the branch
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// target operand. If the machine operand requires relocation,
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// record the relocation and return zero.
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unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getMachineOpValue - Return binary encoding of operand. If the machin
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// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned
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getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const;
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}; // class MipsMCCodeEmitter
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} // namespace
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MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx)
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{
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return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
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}
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MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx)
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{
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return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
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}
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// If the D<shift> instruction has a shift amount that is greater
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// than 31 (checked in calling routine), lower it to a D<shift>32 instruction
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static void LowerLargeShift(MCInst& Inst) {
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assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
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assert(Inst.getOperand(2).isImm());
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int64_t Shift = Inst.getOperand(2).getImm();
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if (Shift <= 31)
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return; // Do nothing
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Shift -= 32;
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// saminus32
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Inst.getOperand(2).setImm(Shift);
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switch (Inst.getOpcode()) {
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default:
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// Calling function is not synchronized
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llvm_unreachable("Unexpected shift instruction");
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case Mips::DSLL:
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Inst.setOpcode(Mips::DSLL32);
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return;
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case Mips::DSRL:
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Inst.setOpcode(Mips::DSRL32);
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return;
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case Mips::DSRA:
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Inst.setOpcode(Mips::DSRA32);
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return;
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case Mips::DROTR:
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Inst.setOpcode(Mips::DROTR32);
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return;
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}
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}
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// Pick a DEXT or DINS instruction variant based on the pos and size operands
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static void LowerDextDins(MCInst& InstIn) {
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int Opcode = InstIn.getOpcode();
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if (Opcode == Mips::DEXT)
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assert(InstIn.getNumOperands() == 4 &&
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"Invalid no. of machine operands for DEXT!");
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else // Only DEXT and DINS are possible
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assert(InstIn.getNumOperands() == 5 &&
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"Invalid no. of machine operands for DINS!");
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assert(InstIn.getOperand(2).isImm());
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int64_t pos = InstIn.getOperand(2).getImm();
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assert(InstIn.getOperand(3).isImm());
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int64_t size = InstIn.getOperand(3).getImm();
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if (size <= 32) {
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if (pos < 32) // DEXT/DINS, do nothing
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return;
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// DEXTU/DINSU
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InstIn.getOperand(2).setImm(pos - 32);
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InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
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return;
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}
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// DEXTM/DINSM
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assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
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InstIn.getOperand(3).setImm(size - 32);
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InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
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return;
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}
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/// EncodeInstruction - Emit the instruction.
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/// Size the instruction with Desc.getSize().
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void MipsMCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const
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{
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// Non-pseudo instructions that get changed for direct object
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// only based on operand values.
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// If this list of instructions get much longer we will move
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// the check to a function call. Until then, this is more efficient.
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MCInst TmpInst = MI;
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switch (MI.getOpcode()) {
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// If shift amount is >= 32 it the inst needs to be lowered further
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case Mips::DSLL:
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case Mips::DSRL:
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case Mips::DSRA:
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case Mips::DROTR:
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LowerLargeShift(TmpInst);
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break;
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// Double extract instruction is chosen by pos and size operands
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case Mips::DEXT:
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case Mips::DINS:
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LowerDextDins(TmpInst);
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}
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unsigned long N = Fixups.size();
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uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups);
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// Check for unimplemented opcodes.
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// Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
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// so we have to special check for them.
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unsigned Opcode = TmpInst.getOpcode();
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if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
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llvm_unreachable("unimplemented opcode in EncodeInstruction()");
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if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
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int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
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if (NewOpcode != -1) {
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if (Fixups.size() > N)
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Fixups.pop_back();
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Opcode = NewOpcode;
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TmpInst.setOpcode (NewOpcode);
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Binary = getBinaryCodeForInstr(TmpInst, Fixups);
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}
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}
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const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
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// Get byte count of instruction
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unsigned Size = Desc.getSize();
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if (!Size)
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llvm_unreachable("Desc.getSize() returns 0");
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EmitInstruction(Binary, Size, OS);
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}
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/// getBranchTargetOpValue - Return binary encoding of the branch
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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// If the destination is an immediate, divide by 4.
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if (MO.isImm()) return MO.getImm() >> 2;
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assert(MO.isExpr() &&
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"getBranchTargetOpValue expects only expressions or immediates");
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const MCExpr *Expr = MO.getExpr();
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Fixups.push_back(MCFixup::Create(0, Expr,
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MCFixupKind(Mips::fixup_Mips_PC16)));
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return 0;
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}
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/// getJumpTargetOpValue - Return binary encoding of the jump
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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// If the destination is an immediate, divide by 4.
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if (MO.isImm()) return MO.getImm()>>2;
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assert(MO.isExpr() &&
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"getJumpTargetOpValue expects only expressions or an immediate");
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const MCExpr *Expr = MO.getExpr();
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Fixups.push_back(MCFixup::Create(0, Expr,
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MCFixupKind(Mips::fixup_Mips_26)));
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return 0;
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}
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unsigned MipsMCCodeEmitter::
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getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const {
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int64_t Res;
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if (Expr->EvaluateAsAbsolute(Res))
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return Res;
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MCExpr::ExprKind Kind = Expr->getKind();
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if (Kind == MCExpr::Constant) {
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return cast<MCConstantExpr>(Expr)->getValue();
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}
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if (Kind == MCExpr::Binary) {
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unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups);
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Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups);
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return Res;
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}
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if (Kind == MCExpr::SymbolRef) {
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Mips::Fixups FixupKind = Mips::Fixups(0);
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switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
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default: llvm_unreachable("Unknown fixup kind!");
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break;
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case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
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FixupKind = Mips::fixup_Mips_GPOFF_HI;
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break;
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case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
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FixupKind = Mips::fixup_Mips_GPOFF_LO;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_PAGE
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: Mips::fixup_Mips_GOT_PAGE;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT_OFST :
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_OFST
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: Mips::fixup_Mips_GOT_OFST;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT_DISP :
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_DISP
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: Mips::fixup_Mips_GOT_DISP;
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break;
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case MCSymbolRefExpr::VK_Mips_GPREL:
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FixupKind = Mips::fixup_Mips_GPREL16;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT_CALL:
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_CALL16
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: Mips::fixup_Mips_CALL16;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT16:
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT16
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: Mips::fixup_Mips_GOT_Global;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT:
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT16
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: Mips::fixup_Mips_GOT_Local;
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break;
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case MCSymbolRefExpr::VK_Mips_ABS_HI:
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_HI16
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: Mips::fixup_Mips_HI16;
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break;
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case MCSymbolRefExpr::VK_Mips_ABS_LO:
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_LO16
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: Mips::fixup_Mips_LO16;
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break;
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case MCSymbolRefExpr::VK_Mips_TLSGD:
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FixupKind = Mips::fixup_Mips_TLSGD;
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break;
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case MCSymbolRefExpr::VK_Mips_TLSLDM:
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FixupKind = Mips::fixup_Mips_TLSLDM;
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break;
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case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
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: Mips::fixup_Mips_DTPREL_HI;
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break;
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case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
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: Mips::fixup_Mips_DTPREL_LO;
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break;
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case MCSymbolRefExpr::VK_Mips_GOTTPREL:
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FixupKind = Mips::fixup_Mips_GOTTPREL;
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break;
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case MCSymbolRefExpr::VK_Mips_TPREL_HI:
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
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: Mips::fixup_Mips_TPREL_HI;
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break;
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case MCSymbolRefExpr::VK_Mips_TPREL_LO:
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FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
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: Mips::fixup_Mips_TPREL_LO;
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break;
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case MCSymbolRefExpr::VK_Mips_HIGHER:
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FixupKind = Mips::fixup_Mips_HIGHER;
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break;
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case MCSymbolRefExpr::VK_Mips_HIGHEST:
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FixupKind = Mips::fixup_Mips_HIGHEST;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT_HI16:
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FixupKind = Mips::fixup_Mips_GOT_HI16;
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break;
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case MCSymbolRefExpr::VK_Mips_GOT_LO16:
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FixupKind = Mips::fixup_Mips_GOT_LO16;
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break;
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case MCSymbolRefExpr::VK_Mips_CALL_HI16:
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FixupKind = Mips::fixup_Mips_CALL_HI16;
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break;
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case MCSymbolRefExpr::VK_Mips_CALL_LO16:
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FixupKind = Mips::fixup_Mips_CALL_LO16;
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break;
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} // switch
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Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
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return 0;
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}
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return 0;
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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unsigned Reg = MO.getReg();
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unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
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return RegNo;
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} else if (MO.isImm()) {
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return static_cast<unsigned>(MO.getImm());
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} else if (MO.isFPImm()) {
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return static_cast<unsigned>(APFloat(MO.getFPImm())
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.bitcastToAPInt().getHiBits(32).getLimitedValue());
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}
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// MO must be an Expr.
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assert(MO.isExpr());
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return getExprOpValue(MO.getExpr(),Fixups);
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}
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/// getMemEncoding - Return binary encoding of memory related operand.
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/// If the offset operand requires relocation, record the relocation.
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unsigned
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MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
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assert(MI.getOperand(OpNo).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
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unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
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return (OffBits & 0xFFFF) | RegBits;
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}
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unsigned MipsMCCodeEmitter::
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getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
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assert(MI.getOperand(OpNo).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) << 16;
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unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
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return (OffBits & 0x0FFF) | RegBits;
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}
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unsigned
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MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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assert(MI.getOperand(OpNo).isImm());
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unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
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return SizeEncoding - 1;
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}
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// FIXME: should be called getMSBEncoding
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//
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unsigned
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MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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assert(MI.getOperand(OpNo-1).isImm());
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assert(MI.getOperand(OpNo).isImm());
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unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
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unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
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return Position + Size - 1;
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}
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#include "MipsGenMCCodeEmitter.inc"
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