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c0b0c677a1
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
2.0 KiB
C++
67 lines
2.0 KiB
C++
//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief TargetRegisterInfo interface that is implemented by all hw codegen
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/// targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUREGISTERINFO_H
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#define AMDGPUREGISTERINFO_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#define GET_REGINFO_ENUM
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#include "AMDGPUGenRegisterInfo.inc"
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namespace llvm {
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class AMDGPUTargetMachine;
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class TargetInstrInfo;
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struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
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TargetMachine &TM;
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const TargetInstrInfo &TII;
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static const uint16_t CalleeSavedReg;
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AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
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virtual BitVector getReservedRegs(const MachineFunction &MF) const {
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assert(!"Unimplemented"); return BitVector();
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}
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/// \param RC is an AMDIL reg class.
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///
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/// \returns The ISA reg class that is equivalent to \p RC.
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virtual const TargetRegisterClass * getISARegClass(
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const TargetRegisterClass * RC) const {
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assert(!"Unimplemented"); return NULL;
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}
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virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
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assert(!"Unimplemented"); return NULL;
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}
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const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const;
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unsigned getFrameRegister(const MachineFunction &MF) const;
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unsigned getIndirectSubReg(unsigned IndirectIndex) const;
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};
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} // End namespace llvm
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#endif // AMDIDSAREGISTERINFO_H
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