Tom Stellard c0b0c677a1 R600: Support for indirect addressing v4 ... Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-06 17:32:29 +00:00
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AMDGPUInstPrinter.cpp	R600: Support for indirect addressing v4	2013-02-06 17:32:29 +00:00
AMDGPUInstPrinter.h	R600: rework handling of the constants	2013-01-23 02:09:06 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile