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556 lines
23 KiB
C++
556 lines
23 KiB
C++
//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MCOperandInfo and MCInstrDesc classes, which
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// are used to describe target instructions and their operands.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCINSTRDESC_H
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#define LLVM_MC_MCINSTRDESC_H
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#include "llvm/Support/DataTypes.h"
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#include <string>
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namespace llvm {
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class MCInst;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class FeatureBitset;
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//===----------------------------------------------------------------------===//
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// Machine Operand Flags and Description
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//===----------------------------------------------------------------------===//
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namespace MCOI {
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// Operand constraints
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enum OperandConstraint {
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TIED_TO = 0, // Must be allocated the same register as.
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EARLY_CLOBBER // Operand is an early clobber register operand
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};
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/// \brief These are flags set on operands, but should be considered
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/// private, all access should go through the MCOperandInfo accessors.
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/// See the accessors for a description of what these are.
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enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef };
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/// \brief Operands are tagged with one of the values of this enum.
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enum OperandType {
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OPERAND_UNKNOWN = 0,
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OPERAND_IMMEDIATE = 1,
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OPERAND_REGISTER = 2,
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OPERAND_MEMORY = 3,
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OPERAND_PCREL = 4,
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OPERAND_FIRST_TARGET = 5
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};
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}
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/// \brief This holds information about one operand of a machine instruction,
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/// indicating the register class for register operands, etc.
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class MCOperandInfo {
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public:
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/// \brief This specifies the register class enumeration of the operand
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/// if the operand is a register. If isLookupPtrRegClass is set, then this is
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/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
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/// get a dynamic register class.
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int16_t RegClass;
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/// \brief These are flags from the MCOI::OperandFlags enum.
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uint8_t Flags;
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/// \brief Information about the type of the operand.
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uint8_t OperandType;
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/// \brief The lower 16 bits are used to specify which constraints are set.
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/// The higher 16 bits are used to specify the value of constraints (4 bits
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/// each).
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uint32_t Constraints;
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/// \brief Set if this operand is a pointer value and it requires a callback
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/// to look up its register class.
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bool isLookupPtrRegClass() const {
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return Flags & (1 << MCOI::LookupPtrRegClass);
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}
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/// \brief Set if this is one of the operands that made up of the predicate
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/// operand that controls an isPredicable() instruction.
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bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
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/// \brief Set if this operand is a optional def.
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bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
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};
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//===----------------------------------------------------------------------===//
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// Machine Instruction Flags and Description
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//===----------------------------------------------------------------------===//
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namespace MCID {
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/// \brief These should be considered private to the implementation of the
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/// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
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/// not use these directly. These all correspond to bitfields in the
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/// MCInstrDesc::Flags field.
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enum Flag {
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Variadic = 0,
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HasOptionalDef,
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Pseudo,
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Return,
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Call,
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Barrier,
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Terminator,
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Branch,
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IndirectBranch,
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Compare,
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MoveImm,
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Bitcast,
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Select,
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DelaySlot,
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FoldableAsLoad,
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MayLoad,
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MayStore,
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Predicable,
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NotDuplicable,
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UnmodeledSideEffects,
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Commutable,
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ConvertibleTo3Addr,
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UsesCustomInserter,
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HasPostISelHook,
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Rematerializable,
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CheapAsAMove,
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ExtraSrcRegAllocReq,
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ExtraDefRegAllocReq,
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RegSequence,
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ExtractSubreg,
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InsertSubreg,
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Convergent
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};
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}
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/// \brief Describe properties that are true of each instruction in the target
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/// description file. This captures information about side effects, register
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/// use and many other things. There is one instance of this struct for each
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/// target instruction class, and the MachineInstr class points to this struct
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/// directly to describe itself.
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class MCInstrDesc {
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public:
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unsigned short Opcode; // The opcode number
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unsigned short NumOperands; // Num of args (may be more if variable_ops)
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unsigned char NumDefs; // Num of args that are definitions
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unsigned char Size; // Number of bytes in encoding.
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unsigned short SchedClass; // enum identifying instr sched class
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uint64_t Flags; // Flags identifying machine instr class
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uint64_t TSFlags; // Target Specific Flag values
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const uint16_t *ImplicitUses; // Registers implicitly read by this instr
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const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
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const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
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// Subtarget feature that this is deprecated on, if any
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// -1 implies this is not deprecated by any single feature. It may still be
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// deprecated due to a "complex" reason, below.
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int64_t DeprecatedFeature;
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// A complex method to determine is a certain is deprecated or not, and return
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// the reason for deprecation.
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bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
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/// \brief Returns the value of the specific constraint if
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/// it is set. Returns -1 if it is not set.
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int getOperandConstraint(unsigned OpNum,
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MCOI::OperandConstraint Constraint) const {
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if (OpNum < NumOperands &&
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(OpInfo[OpNum].Constraints & (1 << Constraint))) {
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unsigned Pos = 16 + Constraint * 4;
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return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
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}
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return -1;
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}
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/// \brief Returns true if a certain instruction is deprecated and if so
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/// returns the reason in \p Info.
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bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
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std::string &Info) const;
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/// \brief Return the opcode number for this descriptor.
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unsigned getOpcode() const { return Opcode; }
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/// \brief Return the number of declared MachineOperands for this
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/// MachineInstruction. Note that variadic (isVariadic() returns true)
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/// instructions may have additional operands at the end of the list, and note
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/// that the machine instruction may include implicit register def/uses as
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/// well.
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unsigned getNumOperands() const { return NumOperands; }
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/// \brief Return the number of MachineOperands that are register
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/// definitions. Register definitions always occur at the start of the
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/// machine operand list. This is the number of "outs" in the .td file,
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/// and does not include implicit defs.
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unsigned getNumDefs() const { return NumDefs; }
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/// \brief Return flags of this instruction.
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unsigned getFlags() const { return Flags; }
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/// \brief Return true if this instruction can have a variable number of
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/// operands. In this case, the variable operands will be after the normal
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/// operands but before the implicit definitions and uses (if any are
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/// present).
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bool isVariadic() const { return Flags & (1 << MCID::Variadic); }
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/// \brief Set if this instruction has an optional definition, e.g.
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/// ARM instructions which can set condition code if 's' bit is set.
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bool hasOptionalDef() const { return Flags & (1 << MCID::HasOptionalDef); }
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/// \brief Return true if this is a pseudo instruction that doesn't
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/// correspond to a real machine instruction.
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bool isPseudo() const { return Flags & (1 << MCID::Pseudo); }
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/// \brief Return true if the instruction is a return.
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bool isReturn() const { return Flags & (1 << MCID::Return); }
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/// \brief Return true if the instruction is a call.
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bool isCall() const { return Flags & (1 << MCID::Call); }
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/// \brief Returns true if the specified instruction stops control flow
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/// from executing the instruction immediately following it. Examples include
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/// unconditional branches and return instructions.
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bool isBarrier() const { return Flags & (1 << MCID::Barrier); }
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/// \brief Returns true if this instruction part of the terminator for
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/// a basic block. Typically this is things like return and branch
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/// instructions.
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///
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/// Various passes use this to insert code into the bottom of a basic block,
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/// but before control flow occurs.
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bool isTerminator() const { return Flags & (1 << MCID::Terminator); }
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/// \brief Returns true if this is a conditional, unconditional, or
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/// indirect branch. Predicates below can be used to discriminate between
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/// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
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/// get more information.
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bool isBranch() const { return Flags & (1 << MCID::Branch); }
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/// \brief Return true if this is an indirect branch, such as a
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/// branch through a register.
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bool isIndirectBranch() const { return Flags & (1 << MCID::IndirectBranch); }
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/// \brief Return true if this is a branch which may fall
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/// through to the next instruction or may transfer control flow to some other
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/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
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/// information about this branch.
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bool isConditionalBranch() const {
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return isBranch() & !isBarrier() & !isIndirectBranch();
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}
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/// \brief Return true if this is a branch which always
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/// transfers control flow to some other block. The
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/// TargetInstrInfo::AnalyzeBranch method can be used to get more information
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/// about this branch.
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bool isUnconditionalBranch() const {
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return isBranch() & isBarrier() & !isIndirectBranch();
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}
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/// \brief Return true if this is a branch or an instruction which directly
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/// writes to the program counter. Considered 'may' affect rather than
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/// 'does' affect as things like predication are not taken into account.
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bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
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/// \brief Return true if this instruction has a predicate operand
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/// that controls execution. It may be set to 'always', or may be set to other
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/// values. There are various methods in TargetInstrInfo that can be used to
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/// control and modify the predicate in this instruction.
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bool isPredicable() const { return Flags & (1 << MCID::Predicable); }
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/// \brief Return true if this instruction is a comparison.
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bool isCompare() const { return Flags & (1 << MCID::Compare); }
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/// \brief Return true if this instruction is a move immediate
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/// (including conditional moves) instruction.
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bool isMoveImmediate() const { return Flags & (1 << MCID::MoveImm); }
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/// \brief Return true if this instruction is a bitcast instruction.
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bool isBitcast() const { return Flags & (1 << MCID::Bitcast); }
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/// \brief Return true if this is a select instruction.
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bool isSelect() const { return Flags & (1 << MCID::Select); }
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/// \brief Return true if this instruction cannot be safely
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/// duplicated. For example, if the instruction has a unique labels attached
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/// to it, duplicating it would cause multiple definition errors.
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bool isNotDuplicable() const { return Flags & (1 << MCID::NotDuplicable); }
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/// \brief Returns true if the specified instruction has a delay slot which
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/// must be filled by the code generator.
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bool hasDelaySlot() const { return Flags & (1 << MCID::DelaySlot); }
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/// \brief Return true for instructions that can be folded as memory operands
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/// in other instructions. The most common use for this is instructions that
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/// are simple loads from memory that don't modify the loaded value in any
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/// way, but it can also be used for instructions that can be expressed as
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/// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
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/// folded when it is beneficial. This should only be set on instructions
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/// that return a value in their only virtual register definition.
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bool canFoldAsLoad() const { return Flags & (1 << MCID::FoldableAsLoad); }
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/// \brief Return true if this instruction behaves
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/// the same way as the generic REG_SEQUENCE instructions.
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/// E.g., on ARM,
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/// dX VMOVDRR rY, rZ
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/// is equivalent to
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/// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
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///
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/// Note that for the optimizers to be able to take advantage of
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/// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
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/// override accordingly.
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bool isRegSequenceLike() const { return Flags & (1 << MCID::RegSequence); }
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/// \brief Return true if this instruction behaves
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/// the same way as the generic EXTRACT_SUBREG instructions.
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/// E.g., on ARM,
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/// rX, rY VMOVRRD dZ
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/// is equivalent to two EXTRACT_SUBREG:
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/// rX = EXTRACT_SUBREG dZ, ssub_0
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/// rY = EXTRACT_SUBREG dZ, ssub_1
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///
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/// Note that for the optimizers to be able to take advantage of
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/// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
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/// override accordingly.
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bool isExtractSubregLike() const {
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return Flags & (1 << MCID::ExtractSubreg);
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}
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/// \brief Return true if this instruction behaves
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/// the same way as the generic INSERT_SUBREG instructions.
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/// E.g., on ARM,
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/// dX = VSETLNi32 dY, rZ, Imm
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/// is equivalent to a INSERT_SUBREG:
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/// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
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///
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/// Note that for the optimizers to be able to take advantage of
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/// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
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/// override accordingly.
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bool isInsertSubregLike() const { return Flags & (1 << MCID::InsertSubreg); }
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/// \brief Return true if this instruction is convergent.
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///
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/// Convergent instructions may only be moved to locations that are
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/// control-equivalent to their original positions.
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bool isConvergent() const { return Flags & (1 << MCID::Convergent); }
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//===--------------------------------------------------------------------===//
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// Side Effect Analysis
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//===--------------------------------------------------------------------===//
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/// \brief Return true if this instruction could possibly read memory.
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/// Instructions with this flag set are not necessarily simple load
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/// instructions, they may load a value and modify it, for example.
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bool mayLoad() const { return Flags & (1 << MCID::MayLoad); }
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/// \brief Return true if this instruction could possibly modify memory.
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/// Instructions with this flag set are not necessarily simple store
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/// instructions, they may store a modified value based on their operands, or
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/// may not actually modify anything, for example.
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bool mayStore() const { return Flags & (1 << MCID::MayStore); }
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/// \brief Return true if this instruction has side
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/// effects that are not modeled by other flags. This does not return true
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/// for instructions whose effects are captured by:
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///
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/// 1. Their operand list and implicit definition/use list. Register use/def
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/// info is explicit for instructions.
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/// 2. Memory accesses. Use mayLoad/mayStore.
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/// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
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///
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/// Examples of side effects would be modifying 'invisible' machine state like
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/// a control register, flushing a cache, modifying a register invisible to
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/// LLVM, etc.
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bool hasUnmodeledSideEffects() const {
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return Flags & (1 << MCID::UnmodeledSideEffects);
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}
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//===--------------------------------------------------------------------===//
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// Flags that indicate whether an instruction can be modified by a method.
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//===--------------------------------------------------------------------===//
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/// \brief Return true if this may be a 2- or 3-address instruction (of the
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/// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
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/// exchanged. If this flag is set, then the
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/// TargetInstrInfo::commuteInstruction method may be used to hack on the
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/// instruction.
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///
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/// Note that this flag may be set on instructions that are only commutable
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/// sometimes. In these cases, the call to commuteInstruction will fail.
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/// Also note that some instructions require non-trivial modification to
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/// commute them.
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bool isCommutable() const { return Flags & (1 << MCID::Commutable); }
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/// \brief Return true if this is a 2-address instruction which can be changed
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/// into a 3-address instruction if needed. Doing this transformation can be
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/// profitable in the register allocator, because it means that the
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/// instruction can use a 2-address form if possible, but degrade into a less
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/// efficient form if the source and dest register cannot be assigned to the
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/// same register. For example, this allows the x86 backend to turn a "shl
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/// reg, 3" instruction into an LEA instruction, which is the same speed as
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/// the shift but has bigger code size.
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///
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/// If this returns true, then the target must implement the
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/// TargetInstrInfo::convertToThreeAddress method for this instruction, which
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/// is allowed to fail if the transformation isn't valid for this specific
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/// instruction (e.g. shl reg, 4 on x86).
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///
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bool isConvertibleTo3Addr() const {
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return Flags & (1 << MCID::ConvertibleTo3Addr);
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}
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/// \brief Return true if this instruction requires custom insertion support
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/// when the DAG scheduler is inserting it into a machine basic block. If
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/// this is true for the instruction, it basically means that it is a pseudo
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/// instruction used at SelectionDAG time that is expanded out into magic code
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/// by the target when MachineInstrs are formed.
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///
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/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
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/// is used to insert this into the MachineBasicBlock.
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bool usesCustomInsertionHook() const {
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return Flags & (1 << MCID::UsesCustomInserter);
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}
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/// \brief Return true if this instruction requires *adjustment* after
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/// instruction selection by calling a target hook. For example, this can be
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/// used to fill in ARM 's' optional operand depending on whether the
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/// conditional flag register is used.
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bool hasPostISelHook() const { return Flags & (1 << MCID::HasPostISelHook); }
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/// \brief Returns true if this instruction is a candidate for remat. This
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/// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
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///
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/// If this flag is set, the isReallyTriviallyReMaterializable()
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/// or isReallyTriviallyReMaterializableGeneric methods are called to verify
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/// the instruction is really rematable.
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bool isRematerializable() const {
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return Flags & (1 << MCID::Rematerializable);
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}
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/// \brief Returns true if this instruction has the same cost (or less) than a
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/// move instruction. This is useful during certain types of optimizations
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/// (e.g., remat during two-address conversion or machine licm) where we would
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/// like to remat or hoist the instruction, but not if it costs more than
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/// moving the instruction into the appropriate register. Note, we are not
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/// marking copies from and to the same register class with this flag.
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///
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/// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
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/// for different subtargets.
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bool isAsCheapAsAMove() const { return Flags & (1 << MCID::CheapAsAMove); }
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/// \brief Returns true if this instruction source operands have special
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/// register allocation requirements that are not captured by the operand
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/// register classes. e.g. ARM::STRD's two source registers must be an even /
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/// odd pair, ARM::STM registers have to be in ascending order. Post-register
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/// allocation passes should not attempt to change allocations for sources of
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/// instructions with this flag.
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bool hasExtraSrcRegAllocReq() const {
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return Flags & (1 << MCID::ExtraSrcRegAllocReq);
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}
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/// \brief Returns true if this instruction def operands have special register
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/// allocation requirements that are not captured by the operand register
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/// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
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/// ARM::LDM registers have to be in ascending order. Post-register
|
|
/// allocation passes should not attempt to change allocations for definitions
|
|
/// of instructions with this flag.
|
|
bool hasExtraDefRegAllocReq() const {
|
|
return Flags & (1 << MCID::ExtraDefRegAllocReq);
|
|
}
|
|
|
|
/// \brief Return a list of registers that are potentially read by any
|
|
/// instance of this machine instruction. For example, on X86, the "adc"
|
|
/// instruction adds two register operands and adds the carry bit in from the
|
|
/// flags register. In this case, the instruction is marked as implicitly
|
|
/// reading the flags. Likewise, the variable shift instruction on X86 is
|
|
/// marked as implicitly reading the 'CL' register, which it always does.
|
|
///
|
|
/// This method returns null if the instruction has no implicit uses.
|
|
const uint16_t *getImplicitUses() const { return ImplicitUses; }
|
|
|
|
/// \brief Return the number of implicit uses this instruction has.
|
|
unsigned getNumImplicitUses() const {
|
|
if (!ImplicitUses)
|
|
return 0;
|
|
unsigned i = 0;
|
|
for (; ImplicitUses[i]; ++i) /*empty*/
|
|
;
|
|
return i;
|
|
}
|
|
|
|
/// \brief Return a list of registers that are potentially written by any
|
|
/// instance of this machine instruction. For example, on X86, many
|
|
/// instructions implicitly set the flags register. In this case, they are
|
|
/// marked as setting the FLAGS. Likewise, many instructions always deposit
|
|
/// their result in a physical register. For example, the X86 divide
|
|
/// instruction always deposits the quotient and remainder in the EAX/EDX
|
|
/// registers. For that instruction, this will return a list containing the
|
|
/// EAX/EDX/EFLAGS registers.
|
|
///
|
|
/// This method returns null if the instruction has no implicit defs.
|
|
const uint16_t *getImplicitDefs() const { return ImplicitDefs; }
|
|
|
|
/// \brief Return the number of implicit defs this instruct has.
|
|
unsigned getNumImplicitDefs() const {
|
|
if (!ImplicitDefs)
|
|
return 0;
|
|
unsigned i = 0;
|
|
for (; ImplicitDefs[i]; ++i) /*empty*/
|
|
;
|
|
return i;
|
|
}
|
|
|
|
/// \brief Return true if this instruction implicitly
|
|
/// uses the specified physical register.
|
|
bool hasImplicitUseOfPhysReg(unsigned Reg) const {
|
|
if (const uint16_t *ImpUses = ImplicitUses)
|
|
for (; *ImpUses; ++ImpUses)
|
|
if (*ImpUses == Reg)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
/// \brief Return true if this instruction implicitly
|
|
/// defines the specified physical register.
|
|
bool hasImplicitDefOfPhysReg(unsigned Reg,
|
|
const MCRegisterInfo *MRI = nullptr) const;
|
|
|
|
/// \brief Return the scheduling class for this instruction. The
|
|
/// scheduling class is an index into the InstrItineraryData table. This
|
|
/// returns zero if there is no known scheduling information for the
|
|
/// instruction.
|
|
unsigned getSchedClass() const { return SchedClass; }
|
|
|
|
/// \brief Return the number of bytes in the encoding of this instruction,
|
|
/// or zero if the encoding size cannot be known from the opcode.
|
|
unsigned getSize() const { return Size; }
|
|
|
|
/// \brief Find the index of the first operand in the
|
|
/// operand list that is used to represent the predicate. It returns -1 if
|
|
/// none is found.
|
|
int findFirstPredOperandIdx() const {
|
|
if (isPredicable()) {
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
|
|
if (OpInfo[i].isPredicate())
|
|
return i;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
private:
|
|
|
|
/// \brief Return true if this instruction defines the specified physical
|
|
/// register, either explicitly or implicitly.
|
|
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
|
|
const MCRegisterInfo &RI) const;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|