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As the AggressiveAntiDepBreaker iterated backward through a scheduling region, we must leave super registers live through subregister definitions so that all relevant subregister definitions are renamed together. The problem was that we were also discarding sub-register use locations as the sub-registers are redefined. The result is that we'd rename the super register along with some, but not all, subregister definitions. R0_D = {R0_L, R1_L} R0_L = {R0_S, R1_S} %R0_L<def> = TRLi9 16, pred:8, pred:%noreg %R1_L<def> = LSRLrr %R1_L<kill>, %R0_S, pred:8, pred:%noreg %R0_L<def> = LSRLrr %R2_L, %R0_S, pred:8, pred:%noreg, %R0_L<imp-use,kill> %R1_L<def> = ANDLri %R1_L<kill>, 2047, pred:8, pred:%noreg %R0_L<def> = ANDLri %R0_L<kill>, 2047, pred:8, pred:%noreg %R4_D<def> = ASRDrr %R0_D<kill>, %R6_S Anti: %R4_D<def> = ASRDrr %R0_D<kill>, %R6_S Def Groups: R4_D=g213->g215(via R4_S)->g214(via R4_L)->g216(via R5_S)->g216(via R4_L)->g217(via R5_L) Use Groups: R0_D=g0->g218(last-use) R1_L->g219(last-use) R6_S=g204->g220(last-use) Anti: %R0_L<def> = ANDLri %R0_L<kill>, 2047, pred:8, pred:%noreg Def Groups: R0_L=g208->g209(via R0_S)->g218(via R0_D)->g210(via R1_S)->g210(via R0_D) Antidep reg: R0_L (real dependency) Use Groups: R0_L=g210->g224(last-use) R0_S->g225(last-use) R1_S->g226(last-use) Anti: %R1_L<def> = ANDLri %R1_L<kill>, 2047, pred:8, pred:%noreg Def Groups: R1_L=g219->g210(via R0_D) Antidep reg: R1_L (real dependency) Use Groups: R1_L=g210->g229(last-use) Anti: %R0_L<def> = LSRLrr %R2_L, %R0_S, pred:8, pred:%noreg, %R0_L<imp-use,kill> Def Groups: R0_L=g224->g225(via R0_S)->g210(via R0_D)->g226(via R1_S)->g226(via R0_D) Antidep reg: R0_L Use Groups: R2_L=g192 R0_S=g226->g230(last-use) R0_L=g226->g231(last-use) R1_S->g232(last-use) Anti: %R1_L<def> = LSRLrr %R1_L<kill>, %R0_S, pred:8, pred:%noreg Def Groups: R1_L=g229->g226(via R0_D) Antidep reg: R1_L Use Groups: R1_L=g226->g233(last-use) R0_S=g230 Anti: %R0_L<def> = TRLi9 16, pred:8, pred:%noreg Def Groups: R0_L=g231->g230(via R0_S)->g226(via R0_D)->g232(via R1_S)->g232(via R0_D) Antidep reg: R0_L Rename Candidates for Group g232: R0_D: elcInt64Regs :: R0_D R1_D R2_D R3_D R4_D R5_D R8_D R9_D R10_D R11_D R12_D R13_D R14_D R15_D R16_D R17_D R18_D R19_D R20_D R21_D R22_D R23_D R24_D R25_D R0_L: elcIntRegs :: R0_L R1_L R2_L R3_L R4_L R5_L R8_L R9_L R10_L R11_L R12_L R13_L R14_L R15_L R16_L R17_L R18_L R19_L R20_L R21_L R22_L R23_L R24_L R25_L R0_S: elcShrtRegs elcShrtRegs :: R0_S R1_S R2_S R3_S R4_S R5_S R8_S R9_S R10_S R11_S R12_S R13_S R14_S R15_S R16_S R17_S R18_S R19_S R20_S R21_S R22_S R23_S R24_S R25_S Find Registers: [R12_D: R12_D R12_L R12_S] Breaking anti-dependence edge on R0_L: R0_D->R12_D(1 refs) R0_L->R12_L(2 refs) R0_S->R12_S(2 refs) Use Groups: ... %R12_L<def> = TRLi9 16, pred:8, pred:%noreg %R1_L<def> = LSRLrr %R1_L<kill>, %R12_S, pred:8, pred:%noreg %R0_L<def> = LSRLrr %R2_L<kill>, %R12_S, pred:8, pred:%noreg, %R12_L<imp-use> %R1_L<def> = ANDLri %R1_L<kill>, 2047, pred:8, pred:%noreg %R0_L<def> = ANDLri %R0_L<kill>, 2047, pred:8, pred:%noreg %R4_D<def> = ASRDrr %R12_D<kill>, %R6_S With this change, we now produce: Anti: %R4_D<def> = ASRDrr %R0_D<kill>, %R6_S Def Groups: R4_D=g213->g215(via R4_S)->g214(via R4_L)->g216(via R5_S)->g216(via R4_L)->g217(via R5_L) Use Groups: R0_D=g0->g218(last-use) R1_L->g219(last-use) R6_S=g204->g220(last-use) Anti: %R0_L<def> = ANDLri %R0_L<kill>, 2047, pred:8, pred:%noreg Def Groups: R0_L=g208->g209(via R0_S)->g218(via R0_D)->g210(via R1_S)->g210(via R0_D) Antidep reg: R0_L (real dependency) Use Groups: R0_L=g210 Anti: %R1_L<def> = ANDLri %R1_L<kill>, 2047, pred:8, pred:%noreg Def Groups: R1_L=g219->g210(via R0_D) Antidep reg: R1_L (real dependency) Use Groups: R1_L=g210 Anti: %R0_L<def> = LSRLrr %R2_L, %R0_S, pred:8, pred:%noreg, %R0_L<imp-use,kill> Def Groups: R0_L=g210->g210(via R0_D)->g210(via R0_D) Antidep reg: R0_L Use Groups: R2_L=g192 R0_S=g210 R0_L=g210 Anti: %R1_L<def> = LSRLrr %R1_L<kill>, %R0_S, pred:8, pred:%noreg Def Groups: R1_L=g210->g210(via R0_D) Antidep reg: R1_L Use Groups: R1_L=g210 R0_S=g210 Anti: %R0_L<def> = TRLi9 16, pred:8, pred:%noreg Def Groups: R0_L=g210->g210(via R0_D)->g210(via R0_D) Antidep reg: R0_L Rename Candidates for Group g210: R0_D: elcInt64Regs :: R0_D R1_D R2_D R3_D R4_D R5_D R8_D R9_D R10_D R11_D R12_D R13_D R14_D R15_D R16_D R17_D R18_D R19_D R20_D R21_D R22_D R23_D R24_D R25_D R0_L: elcIntRegs elcIntAIRegs elcIntRegs elcIntRegs elcIntRegs elcIntRegs :: R0_L R1_L R2_L R3_L R4_L R5_L R8_L R9_L R10_L R11_L R12_L R13_L R14_L R15_L R16_L R17_L R18_L R19_L R20_L R21_L R22_L R23_L R24_L R25_L R1_L: elcIntRegs elcIntRegs elcIntRegs elcIntRegs elcIntRegs :: R0_L R1_L R2_L R3_L R4_L R5_L R8_L R9_L R10_L R11_L R12_L R13_L R14_L R15_L R16_L R17_L R18_L R19_L R20_L R21_L R22_L R23_L R24_L R25_L R0_S: elcShrtRegs elcShrtRegs :: R0_S R1_S R2_S R3_S R4_S R5_S R8_S R9_S R10_S R11_S R12_S R13_S R14_S R15_S R16_S R17_S R18_S R19_S R20_S R21_S R22_S R23_S R24_S R25_S Find Registers: [R12_D: R12_D R12_L R13_L R12_S] Breaking anti-dependence edge on R0_L: R0_D->R12_D(1 refs) R0_L->R12_L(7 refs) R1_L->R13_L(5 refs) R0_S->R12_S(2 refs) Use Groups: ... %R12_L<def> = TRLi9 16, pred:8, pred:%noreg %R13_L<def> = LSRLrr %R13_L<kill>, %R12_S, pred:8, pred:%noreg %R12_L<def> = LSRLrr %R2_L<kill>, %R12_S<kill>, pred:8, pred:%noreg, %R12_L<imp-use,kill> %R13_L<def> = ANDLri %R13_L<kill>, 2047, pred:8, pred:%noreg %R12_L<def> = ANDLri %R12_L<kill>, 2047, pred:8, pred:%noreg %R4_D<def> = ASRDrr %R12_D, %R6_S, %R12_L<imp-def>, %R12_S<imp-def>, %R13_S<imp-def> As demonstrated by this example, this is also somewhat unfortunate, because there is actually no need to rename the super register in this case (it is fully covered by later subregister definitions), but we don't seem to track enough information here to exploit that either. Thanks to Daniil Troshkov for reporting the issue. The debug outputs in this commit message are from Daniil. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227311 91177308-0d34-0410-b5e6-96231b3b80d8
971 lines
35 KiB
C++
971 lines
35 KiB
C++
//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AggressiveAntiDepBreaker class, which
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// implements register anti-dependence breaking during post-RA
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// scheduling. It attempts to break all anti-dependencies within a
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// block.
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//
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//===----------------------------------------------------------------------===//
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#include "AggressiveAntiDepBreaker.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "post-RA-sched"
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// If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
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static cl::opt<int>
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DebugDiv("agg-antidep-debugdiv",
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cl::desc("Debug control for aggressive anti-dep breaker"),
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cl::init(0), cl::Hidden);
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static cl::opt<int>
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DebugMod("agg-antidep-debugmod",
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cl::desc("Debug control for aggressive anti-dep breaker"),
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cl::init(0), cl::Hidden);
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AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
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MachineBasicBlock *BB) :
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NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
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GroupNodeIndices(TargetRegs, 0),
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KillIndices(TargetRegs, 0),
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DefIndices(TargetRegs, 0)
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{
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const unsigned BBSize = BB->size();
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for (unsigned i = 0; i < NumTargetRegs; ++i) {
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// Initialize all registers to be in their own group. Initially we
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// assign the register to the same-indexed GroupNode.
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GroupNodeIndices[i] = i;
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// Initialize the indices to indicate that no registers are live.
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KillIndices[i] = ~0u;
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DefIndices[i] = BBSize;
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}
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}
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unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
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unsigned Node = GroupNodeIndices[Reg];
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while (GroupNodes[Node] != Node)
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Node = GroupNodes[Node];
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return Node;
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}
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void AggressiveAntiDepState::GetGroupRegs(
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unsigned Group,
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std::vector<unsigned> &Regs,
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
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{
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for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
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if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
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Regs.push_back(Reg);
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}
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}
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unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
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{
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assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
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assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
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// find group for each register
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unsigned Group1 = GetGroup(Reg1);
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unsigned Group2 = GetGroup(Reg2);
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// if either group is 0, then that must become the parent
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unsigned Parent = (Group1 == 0) ? Group1 : Group2;
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unsigned Other = (Parent == Group1) ? Group2 : Group1;
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GroupNodes.at(Other) = Parent;
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return Parent;
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}
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unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
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{
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// Create a new GroupNode for Reg. Reg's existing GroupNode must
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// stay as is because there could be other GroupNodes referring to
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// it.
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unsigned idx = GroupNodes.size();
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GroupNodes.push_back(idx);
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GroupNodeIndices[Reg] = idx;
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return idx;
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}
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bool AggressiveAntiDepState::IsLive(unsigned Reg)
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{
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// KillIndex must be defined and DefIndex not defined for a register
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// to be live.
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return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
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}
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AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(
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MachineFunction &MFi, const RegisterClassInfo &RCI,
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TargetSubtargetInfo::RegClassVector &CriticalPathRCs)
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: AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
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TII(MF.getSubtarget().getInstrInfo()),
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TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
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State(nullptr) {
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/* Collect a bitset of all registers that are only broken if they
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are on the critical path. */
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for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
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BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
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if (CriticalPathSet.none())
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CriticalPathSet = CPSet;
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else
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CriticalPathSet |= CPSet;
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}
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DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
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DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
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r = CriticalPathSet.find_next(r))
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dbgs() << " " << TRI->getName(r));
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DEBUG(dbgs() << '\n');
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}
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AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
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delete State;
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}
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void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
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assert(!State);
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State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
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bool IsReturnBlock = (!BB->empty() && BB->back().isReturn());
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std::vector<unsigned> &KillIndices = State->GetKillIndices();
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std::vector<unsigned> &DefIndices = State->GetDefIndices();
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// Examine the live-in regs of all successors.
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI)
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for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
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E = (*SI)->livein_end(); I != E; ++I) {
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for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
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unsigned Reg = *AI;
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State->UnionGroups(Reg, 0);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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}
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}
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// Mark live-out callee-saved registers. In a return block this is
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// all callee-saved registers. In non-return this is any
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// callee-saved register that is not saved in the prolog.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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BitVector Pristine = MFI->getPristineRegs(BB);
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for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
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unsigned Reg = *I;
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if (!IsReturnBlock && !Pristine.test(Reg)) continue;
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
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unsigned AliasReg = *AI;
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State->UnionGroups(AliasReg, 0);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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}
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void AggressiveAntiDepBreaker::FinishBlock() {
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delete State;
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State = nullptr;
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}
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void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
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unsigned InsertPosIndex) {
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assert(Count < InsertPosIndex && "Instruction index out of expected range!");
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std::set<unsigned> PassthruRegs;
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GetPassthruRegs(MI, PassthruRegs);
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PrescanInstruction(MI, Count, PassthruRegs);
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ScanInstruction(MI, Count);
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DEBUG(dbgs() << "Observe: ");
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DEBUG(MI->dump());
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DEBUG(dbgs() << "\tRegs:");
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std::vector<unsigned> &DefIndices = State->GetDefIndices();
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for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
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// If Reg is current live, then mark that it can't be renamed as
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// we don't know the extent of its live-range anymore (now that it
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// has been scheduled). If it is not live but was defined in the
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// previous schedule region, then set its def index to the most
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// conservative location (i.e. the beginning of the previous
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// schedule region).
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if (State->IsLive(Reg)) {
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DEBUG(if (State->GetGroup(Reg) != 0)
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dbgs() << " " << TRI->getName(Reg) << "=g" <<
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State->GetGroup(Reg) << "->g0(region live-out)");
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State->UnionGroups(Reg, 0);
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} else if ((DefIndices[Reg] < InsertPosIndex)
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&& (DefIndices[Reg] >= Count)) {
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DefIndices[Reg] = Count;
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}
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}
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DEBUG(dbgs() << '\n');
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}
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bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
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MachineOperand& MO)
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{
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if (!MO.isReg() || !MO.isImplicit())
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return false;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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return false;
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MachineOperand *Op = nullptr;
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if (MO.isDef())
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Op = MI->findRegisterUseOperand(Reg, true);
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else
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Op = MI->findRegisterDefOperand(Reg);
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return(Op && Op->isImplicit());
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}
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void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
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std::set<unsigned>& PassthruRegs) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
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IsImplicitDefUse(MI, MO)) {
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const unsigned Reg = MO.getReg();
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for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
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SubRegs.isValid(); ++SubRegs)
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PassthruRegs.insert(*SubRegs);
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}
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}
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}
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/// AntiDepEdges - Return in Edges the anti- and output- dependencies
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/// in SU that we want to consider for breaking.
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static void AntiDepEdges(const SUnit *SU, std::vector<const SDep*>& Edges) {
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SmallSet<unsigned, 4> RegSet;
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for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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P != PE; ++P) {
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if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
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if (RegSet.insert(P->getReg()).second)
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Edges.push_back(&*P);
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}
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}
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}
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/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
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/// critical path.
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static const SUnit *CriticalPathStep(const SUnit *SU) {
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const SDep *Next = nullptr;
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unsigned NextDepth = 0;
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// Find the predecessor edge with the greatest depth.
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if (SU) {
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for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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P != PE; ++P) {
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const SUnit *PredSU = P->getSUnit();
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unsigned PredLatency = P->getLatency();
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unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
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// In the case of a latency tie, prefer an anti-dependency edge over
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// other types of edges.
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if (NextDepth < PredTotalLatency ||
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(NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
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NextDepth = PredTotalLatency;
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Next = &*P;
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}
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}
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}
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return (Next) ? Next->getSUnit() : nullptr;
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}
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void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
|
|
const char *tag,
|
|
const char *header,
|
|
const char *footer) {
|
|
std::vector<unsigned> &KillIndices = State->GetKillIndices();
|
|
std::vector<unsigned> &DefIndices = State->GetDefIndices();
|
|
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
|
|
RegRefs = State->GetRegRefs();
|
|
|
|
// FIXME: We must leave subregisters of live super registers as live, so that
|
|
// we don't clear out the register tracking information for subregisters of
|
|
// super registers we're still tracking (and with which we're unioning
|
|
// subregister definitions).
|
|
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
|
|
if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
|
|
DEBUG(if (!header && footer) dbgs() << footer);
|
|
return;
|
|
}
|
|
|
|
if (!State->IsLive(Reg)) {
|
|
KillIndices[Reg] = KillIdx;
|
|
DefIndices[Reg] = ~0u;
|
|
RegRefs.erase(Reg);
|
|
State->LeaveGroup(Reg);
|
|
DEBUG(if (header) {
|
|
dbgs() << header << TRI->getName(Reg); header = nullptr; });
|
|
DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
|
|
}
|
|
// Repeat for subregisters.
|
|
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
|
|
unsigned SubregReg = *SubRegs;
|
|
if (!State->IsLive(SubregReg)) {
|
|
KillIndices[SubregReg] = KillIdx;
|
|
DefIndices[SubregReg] = ~0u;
|
|
RegRefs.erase(SubregReg);
|
|
State->LeaveGroup(SubregReg);
|
|
DEBUG(if (header) {
|
|
dbgs() << header << TRI->getName(Reg); header = nullptr; });
|
|
DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
|
|
State->GetGroup(SubregReg) << tag);
|
|
}
|
|
}
|
|
|
|
DEBUG(if (!header && footer) dbgs() << footer);
|
|
}
|
|
|
|
void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
|
|
unsigned Count,
|
|
std::set<unsigned>& PassthruRegs) {
|
|
std::vector<unsigned> &DefIndices = State->GetDefIndices();
|
|
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
|
|
RegRefs = State->GetRegRefs();
|
|
|
|
// Handle dead defs by simulating a last-use of the register just
|
|
// after the def. A dead def can occur because the def is truly
|
|
// dead, or because only a subregister is live at the def. If we
|
|
// don't do this the dead def will be incorrectly merged into the
|
|
// previous def.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isDef()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
|
|
HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
|
|
}
|
|
|
|
DEBUG(dbgs() << "\tDef Groups:");
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isDef()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
|
|
DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
|
|
|
|
// If MI's defs have a special allocation requirement, don't allow
|
|
// any def registers to be changed. Also assume all registers
|
|
// defined in a call must not be changed (ABI).
|
|
if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
|
|
TII->isPredicated(MI)) {
|
|
DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
|
|
State->UnionGroups(Reg, 0);
|
|
}
|
|
|
|
// Any aliased that are live at this point are completely or
|
|
// partially defined here, so group those aliases with Reg.
|
|
for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
|
|
unsigned AliasReg = *AI;
|
|
if (State->IsLive(AliasReg)) {
|
|
State->UnionGroups(Reg, AliasReg);
|
|
DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
|
|
TRI->getName(AliasReg) << ")");
|
|
}
|
|
}
|
|
|
|
// Note register reference...
|
|
const TargetRegisterClass *RC = nullptr;
|
|
if (i < MI->getDesc().getNumOperands())
|
|
RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
|
|
AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
|
|
RegRefs.insert(std::make_pair(Reg, RR));
|
|
}
|
|
|
|
DEBUG(dbgs() << '\n');
|
|
|
|
// Scan the register defs for this instruction and update
|
|
// live-ranges.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isDef()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
// Ignore KILLs and passthru registers for liveness...
|
|
if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
|
|
continue;
|
|
|
|
// Update def for Reg and aliases.
|
|
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
|
|
// We need to be careful here not to define already-live super registers.
|
|
// If the super register is already live, then this definition is not
|
|
// a definition of the whole super register (just a partial insertion
|
|
// into it). Earlier subregister definitions (which we've not yet visited
|
|
// because we're iterating bottom-up) need to be linked to the same group
|
|
// as this definition.
|
|
if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
|
|
continue;
|
|
|
|
DefIndices[*AI] = Count;
|
|
}
|
|
}
|
|
}
|
|
|
|
void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
|
|
unsigned Count) {
|
|
DEBUG(dbgs() << "\tUse Groups:");
|
|
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
|
|
RegRefs = State->GetRegRefs();
|
|
|
|
// If MI's uses have special allocation requirement, don't allow
|
|
// any use registers to be changed. Also assume all registers
|
|
// used in a call must not be changed (ABI).
|
|
// FIXME: The issue with predicated instruction is more complex. We are being
|
|
// conservatively here because the kill markers cannot be trusted after
|
|
// if-conversion:
|
|
// %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
|
|
// ...
|
|
// STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
|
|
// %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
|
|
// STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
|
|
//
|
|
// The first R6 kill is not really a kill since it's killed by a predicated
|
|
// instruction which may not be executed. The second R6 def may or may not
|
|
// re-define R6 so it's not safe to change it since the last R6 use cannot be
|
|
// changed.
|
|
bool Special = MI->isCall() ||
|
|
MI->hasExtraSrcRegAllocReq() ||
|
|
TII->isPredicated(MI);
|
|
|
|
// Scan the register uses for this instruction and update
|
|
// live-ranges, groups and RegRefs.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
|
|
DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
|
|
State->GetGroup(Reg));
|
|
|
|
// It wasn't previously live but now it is, this is a kill. Forget
|
|
// the previous live-range information and start a new live-range
|
|
// for the register.
|
|
HandleLastUse(Reg, Count, "(last-use)");
|
|
|
|
if (Special) {
|
|
DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
|
|
State->UnionGroups(Reg, 0);
|
|
}
|
|
|
|
// Note register reference...
|
|
const TargetRegisterClass *RC = nullptr;
|
|
if (i < MI->getDesc().getNumOperands())
|
|
RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
|
|
AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
|
|
RegRefs.insert(std::make_pair(Reg, RR));
|
|
}
|
|
|
|
DEBUG(dbgs() << '\n');
|
|
|
|
// Form a group of all defs and uses of a KILL instruction to ensure
|
|
// that all registers are renamed as a group.
|
|
if (MI->isKill()) {
|
|
DEBUG(dbgs() << "\tKill Group:");
|
|
|
|
unsigned FirstReg = 0;
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
|
|
if (FirstReg != 0) {
|
|
DEBUG(dbgs() << "=" << TRI->getName(Reg));
|
|
State->UnionGroups(FirstReg, Reg);
|
|
} else {
|
|
DEBUG(dbgs() << " " << TRI->getName(Reg));
|
|
FirstReg = Reg;
|
|
}
|
|
}
|
|
|
|
DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
|
|
}
|
|
}
|
|
|
|
BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
|
|
BitVector BV(TRI->getNumRegs(), false);
|
|
bool first = true;
|
|
|
|
// Check all references that need rewriting for Reg. For each, use
|
|
// the corresponding register class to narrow the set of registers
|
|
// that are appropriate for renaming.
|
|
std::pair<std::multimap<unsigned,
|
|
AggressiveAntiDepState::RegisterReference>::iterator,
|
|
std::multimap<unsigned,
|
|
AggressiveAntiDepState::RegisterReference>::iterator>
|
|
Range = State->GetRegRefs().equal_range(Reg);
|
|
for (std::multimap<unsigned,
|
|
AggressiveAntiDepState::RegisterReference>::iterator Q = Range.first,
|
|
QE = Range.second; Q != QE; ++Q) {
|
|
const TargetRegisterClass *RC = Q->second.RC;
|
|
if (!RC) continue;
|
|
|
|
BitVector RCBV = TRI->getAllocatableSet(MF, RC);
|
|
if (first) {
|
|
BV |= RCBV;
|
|
first = false;
|
|
} else {
|
|
BV &= RCBV;
|
|
}
|
|
|
|
DEBUG(dbgs() << " " << TRI->getRegClassName(RC));
|
|
}
|
|
|
|
return BV;
|
|
}
|
|
|
|
bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
|
|
unsigned AntiDepGroupIndex,
|
|
RenameOrderType& RenameOrder,
|
|
std::map<unsigned, unsigned> &RenameMap) {
|
|
std::vector<unsigned> &KillIndices = State->GetKillIndices();
|
|
std::vector<unsigned> &DefIndices = State->GetDefIndices();
|
|
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
|
|
RegRefs = State->GetRegRefs();
|
|
|
|
// Collect all referenced registers in the same group as
|
|
// AntiDepReg. These all need to be renamed together if we are to
|
|
// break the anti-dependence.
|
|
std::vector<unsigned> Regs;
|
|
State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
|
|
assert(Regs.size() > 0 && "Empty register group!");
|
|
if (Regs.size() == 0)
|
|
return false;
|
|
|
|
// Find the "superest" register in the group. At the same time,
|
|
// collect the BitVector of registers that can be used to rename
|
|
// each register.
|
|
DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
|
|
<< ":\n");
|
|
std::map<unsigned, BitVector> RenameRegisterMap;
|
|
unsigned SuperReg = 0;
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
unsigned Reg = Regs[i];
|
|
if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
|
|
SuperReg = Reg;
|
|
|
|
// If Reg has any references, then collect possible rename regs
|
|
if (RegRefs.count(Reg) > 0) {
|
|
DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
|
|
|
|
BitVector BV = GetRenameRegisters(Reg);
|
|
RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
|
|
|
|
DEBUG(dbgs() << " ::");
|
|
DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
|
|
dbgs() << " " << TRI->getName(r));
|
|
DEBUG(dbgs() << "\n");
|
|
}
|
|
}
|
|
|
|
// All group registers should be a subreg of SuperReg.
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
unsigned Reg = Regs[i];
|
|
if (Reg == SuperReg) continue;
|
|
bool IsSub = TRI->isSubRegister(SuperReg, Reg);
|
|
// FIXME: remove this once PR18663 has been properly fixed. For now,
|
|
// return a conservative answer:
|
|
// assert(IsSub && "Expecting group subregister");
|
|
if (!IsSub)
|
|
return false;
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
// If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
|
|
if (DebugDiv > 0) {
|
|
static int renamecnt = 0;
|
|
if (renamecnt++ % DebugDiv != DebugMod)
|
|
return false;
|
|
|
|
dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
|
|
" for debug ***\n";
|
|
}
|
|
#endif
|
|
|
|
// Check each possible rename register for SuperReg in round-robin
|
|
// order. If that register is available, and the corresponding
|
|
// registers are available for the other group subregisters, then we
|
|
// can use those registers to rename.
|
|
|
|
// FIXME: Using getMinimalPhysRegClass is very conservative. We should
|
|
// check every use of the register and find the largest register class
|
|
// that can be used in all of them.
|
|
const TargetRegisterClass *SuperRC =
|
|
TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
|
|
|
|
ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
|
|
if (Order.empty()) {
|
|
DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
|
|
return false;
|
|
}
|
|
|
|
DEBUG(dbgs() << "\tFind Registers:");
|
|
|
|
RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
|
|
|
|
unsigned OrigR = RenameOrder[SuperRC];
|
|
unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
|
|
unsigned R = OrigR;
|
|
do {
|
|
if (R == 0) R = Order.size();
|
|
--R;
|
|
const unsigned NewSuperReg = Order[R];
|
|
// Don't consider non-allocatable registers
|
|
if (!MRI.isAllocatable(NewSuperReg)) continue;
|
|
// Don't replace a register with itself.
|
|
if (NewSuperReg == SuperReg) continue;
|
|
|
|
DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
|
|
RenameMap.clear();
|
|
|
|
// For each referenced group register (which must be a SuperReg or
|
|
// a subregister of SuperReg), find the corresponding subregister
|
|
// of NewSuperReg and make sure it is free to be renamed.
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
unsigned Reg = Regs[i];
|
|
unsigned NewReg = 0;
|
|
if (Reg == SuperReg) {
|
|
NewReg = NewSuperReg;
|
|
} else {
|
|
unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
|
|
if (NewSubRegIdx != 0)
|
|
NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
|
|
}
|
|
|
|
DEBUG(dbgs() << " " << TRI->getName(NewReg));
|
|
|
|
// Check if Reg can be renamed to NewReg.
|
|
BitVector BV = RenameRegisterMap[Reg];
|
|
if (!BV.test(NewReg)) {
|
|
DEBUG(dbgs() << "(no rename)");
|
|
goto next_super_reg;
|
|
}
|
|
|
|
// If NewReg is dead and NewReg's most recent def is not before
|
|
// Regs's kill, it's safe to replace Reg with NewReg. We
|
|
// must also check all aliases of NewReg, because we can't define a
|
|
// register when any sub or super is already live.
|
|
if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
|
|
DEBUG(dbgs() << "(live)");
|
|
goto next_super_reg;
|
|
} else {
|
|
bool found = false;
|
|
for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
|
|
unsigned AliasReg = *AI;
|
|
if (State->IsLive(AliasReg) ||
|
|
(KillIndices[Reg] > DefIndices[AliasReg])) {
|
|
DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
|
|
found = true;
|
|
break;
|
|
}
|
|
}
|
|
if (found)
|
|
goto next_super_reg;
|
|
}
|
|
|
|
// We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
|
|
// defines 'NewReg' via an early-clobber operand.
|
|
auto Range = RegRefs.equal_range(Reg);
|
|
for (auto Q = Range.first, QE = Range.second; Q != QE; ++Q) {
|
|
auto UseMI = Q->second.Operand->getParent();
|
|
int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI);
|
|
if (Idx == -1)
|
|
continue;
|
|
|
|
if (UseMI->getOperand(Idx).isEarlyClobber()) {
|
|
DEBUG(dbgs() << "(ec)");
|
|
goto next_super_reg;
|
|
}
|
|
}
|
|
|
|
// Record that 'Reg' can be renamed to 'NewReg'.
|
|
RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
|
|
}
|
|
|
|
// If we fall-out here, then every register in the group can be
|
|
// renamed, as recorded in RenameMap.
|
|
RenameOrder.erase(SuperRC);
|
|
RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
|
|
DEBUG(dbgs() << "]\n");
|
|
return true;
|
|
|
|
next_super_reg:
|
|
DEBUG(dbgs() << ']');
|
|
} while (R != EndR);
|
|
|
|
DEBUG(dbgs() << '\n');
|
|
|
|
// No registers are free and available!
|
|
return false;
|
|
}
|
|
|
|
/// BreakAntiDependencies - Identifiy anti-dependencies within the
|
|
/// ScheduleDAG and break them by renaming registers.
|
|
///
|
|
unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
|
|
const std::vector<SUnit>& SUnits,
|
|
MachineBasicBlock::iterator Begin,
|
|
MachineBasicBlock::iterator End,
|
|
unsigned InsertPosIndex,
|
|
DbgValueVector &DbgValues) {
|
|
|
|
std::vector<unsigned> &KillIndices = State->GetKillIndices();
|
|
std::vector<unsigned> &DefIndices = State->GetDefIndices();
|
|
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
|
|
RegRefs = State->GetRegRefs();
|
|
|
|
// The code below assumes that there is at least one instruction,
|
|
// so just duck out immediately if the block is empty.
|
|
if (SUnits.empty()) return 0;
|
|
|
|
// For each regclass the next register to use for renaming.
|
|
RenameOrderType RenameOrder;
|
|
|
|
// ...need a map from MI to SUnit.
|
|
std::map<MachineInstr *, const SUnit *> MISUnitMap;
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
const SUnit *SU = &SUnits[i];
|
|
MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
|
|
SU));
|
|
}
|
|
|
|
// Track progress along the critical path through the SUnit graph as
|
|
// we walk the instructions. This is needed for regclasses that only
|
|
// break critical-path anti-dependencies.
|
|
const SUnit *CriticalPathSU = nullptr;
|
|
MachineInstr *CriticalPathMI = nullptr;
|
|
if (CriticalPathSet.any()) {
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
const SUnit *SU = &SUnits[i];
|
|
if (!CriticalPathSU ||
|
|
((SU->getDepth() + SU->Latency) >
|
|
(CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
|
|
CriticalPathSU = SU;
|
|
}
|
|
}
|
|
|
|
CriticalPathMI = CriticalPathSU->getInstr();
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
|
|
DEBUG(dbgs() << "Available regs:");
|
|
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
|
|
if (!State->IsLive(Reg))
|
|
DEBUG(dbgs() << " " << TRI->getName(Reg));
|
|
}
|
|
DEBUG(dbgs() << '\n');
|
|
#endif
|
|
|
|
// Attempt to break anti-dependence edges. Walk the instructions
|
|
// from the bottom up, tracking information about liveness as we go
|
|
// to help determine which registers are available.
|
|
unsigned Broken = 0;
|
|
unsigned Count = InsertPosIndex - 1;
|
|
for (MachineBasicBlock::iterator I = End, E = Begin;
|
|
I != E; --Count) {
|
|
MachineInstr *MI = --I;
|
|
|
|
if (MI->isDebugValue())
|
|
continue;
|
|
|
|
DEBUG(dbgs() << "Anti: ");
|
|
DEBUG(MI->dump());
|
|
|
|
std::set<unsigned> PassthruRegs;
|
|
GetPassthruRegs(MI, PassthruRegs);
|
|
|
|
// Process the defs in MI...
|
|
PrescanInstruction(MI, Count, PassthruRegs);
|
|
|
|
// The dependence edges that represent anti- and output-
|
|
// dependencies that are candidates for breaking.
|
|
std::vector<const SDep *> Edges;
|
|
const SUnit *PathSU = MISUnitMap[MI];
|
|
AntiDepEdges(PathSU, Edges);
|
|
|
|
// If MI is not on the critical path, then we don't rename
|
|
// registers in the CriticalPathSet.
|
|
BitVector *ExcludeRegs = nullptr;
|
|
if (MI == CriticalPathMI) {
|
|
CriticalPathSU = CriticalPathStep(CriticalPathSU);
|
|
CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr;
|
|
} else if (CriticalPathSet.any()) {
|
|
ExcludeRegs = &CriticalPathSet;
|
|
}
|
|
|
|
// Ignore KILL instructions (they form a group in ScanInstruction
|
|
// but don't cause any anti-dependence breaking themselves)
|
|
if (!MI->isKill()) {
|
|
// Attempt to break each anti-dependency...
|
|
for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
|
|
const SDep *Edge = Edges[i];
|
|
SUnit *NextSU = Edge->getSUnit();
|
|
|
|
if ((Edge->getKind() != SDep::Anti) &&
|
|
(Edge->getKind() != SDep::Output)) continue;
|
|
|
|
unsigned AntiDepReg = Edge->getReg();
|
|
DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
|
|
assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
|
|
|
|
if (!MRI.isAllocatable(AntiDepReg)) {
|
|
// Don't break anti-dependencies on non-allocatable registers.
|
|
DEBUG(dbgs() << " (non-allocatable)\n");
|
|
continue;
|
|
} else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
|
|
// Don't break anti-dependencies for critical path registers
|
|
// if not on the critical path
|
|
DEBUG(dbgs() << " (not critical-path)\n");
|
|
continue;
|
|
} else if (PassthruRegs.count(AntiDepReg) != 0) {
|
|
// If the anti-dep register liveness "passes-thru", then
|
|
// don't try to change it. It will be changed along with
|
|
// the use if required to break an earlier antidep.
|
|
DEBUG(dbgs() << " (passthru)\n");
|
|
continue;
|
|
} else {
|
|
// No anti-dep breaking for implicit deps
|
|
MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
|
|
assert(AntiDepOp && "Can't find index for defined register operand");
|
|
if (!AntiDepOp || AntiDepOp->isImplicit()) {
|
|
DEBUG(dbgs() << " (implicit)\n");
|
|
continue;
|
|
}
|
|
|
|
// If the SUnit has other dependencies on the SUnit that
|
|
// it anti-depends on, don't bother breaking the
|
|
// anti-dependency since those edges would prevent such
|
|
// units from being scheduled past each other
|
|
// regardless.
|
|
//
|
|
// Also, if there are dependencies on other SUnits with the
|
|
// same register as the anti-dependency, don't attempt to
|
|
// break it.
|
|
for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
|
|
PE = PathSU->Preds.end(); P != PE; ++P) {
|
|
if (P->getSUnit() == NextSU ?
|
|
(P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
|
|
(P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
|
|
AntiDepReg = 0;
|
|
break;
|
|
}
|
|
}
|
|
for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
|
|
PE = PathSU->Preds.end(); P != PE; ++P) {
|
|
if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
|
|
(P->getKind() != SDep::Output)) {
|
|
DEBUG(dbgs() << " (real dependency)\n");
|
|
AntiDepReg = 0;
|
|
break;
|
|
} else if ((P->getSUnit() != NextSU) &&
|
|
(P->getKind() == SDep::Data) &&
|
|
(P->getReg() == AntiDepReg)) {
|
|
DEBUG(dbgs() << " (other dependency)\n");
|
|
AntiDepReg = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (AntiDepReg == 0) continue;
|
|
}
|
|
|
|
assert(AntiDepReg != 0);
|
|
if (AntiDepReg == 0) continue;
|
|
|
|
// Determine AntiDepReg's register group.
|
|
const unsigned GroupIndex = State->GetGroup(AntiDepReg);
|
|
if (GroupIndex == 0) {
|
|
DEBUG(dbgs() << " (zero group)\n");
|
|
continue;
|
|
}
|
|
|
|
DEBUG(dbgs() << '\n');
|
|
|
|
// Look for a suitable register to use to break the anti-dependence.
|
|
std::map<unsigned, unsigned> RenameMap;
|
|
if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
|
|
DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
|
|
<< TRI->getName(AntiDepReg) << ":");
|
|
|
|
// Handle each group register...
|
|
for (std::map<unsigned, unsigned>::iterator
|
|
S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
|
|
unsigned CurrReg = S->first;
|
|
unsigned NewReg = S->second;
|
|
|
|
DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
|
|
TRI->getName(NewReg) << "(" <<
|
|
RegRefs.count(CurrReg) << " refs)");
|
|
|
|
// Update the references to the old register CurrReg to
|
|
// refer to the new register NewReg.
|
|
std::pair<std::multimap<unsigned,
|
|
AggressiveAntiDepState::RegisterReference>::iterator,
|
|
std::multimap<unsigned,
|
|
AggressiveAntiDepState::RegisterReference>::iterator>
|
|
Range = RegRefs.equal_range(CurrReg);
|
|
for (std::multimap<unsigned,
|
|
AggressiveAntiDepState::RegisterReference>::iterator
|
|
Q = Range.first, QE = Range.second; Q != QE; ++Q) {
|
|
Q->second.Operand->setReg(NewReg);
|
|
// If the SU for the instruction being updated has debug
|
|
// information related to the anti-dependency register, make
|
|
// sure to update that as well.
|
|
const SUnit *SU = MISUnitMap[Q->second.Operand->getParent()];
|
|
if (!SU) continue;
|
|
for (DbgValueVector::iterator DVI = DbgValues.begin(),
|
|
DVE = DbgValues.end(); DVI != DVE; ++DVI)
|
|
if (DVI->second == Q->second.Operand->getParent())
|
|
UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
|
|
}
|
|
|
|
// We just went back in time and modified history; the
|
|
// liveness information for CurrReg is now inconsistent. Set
|
|
// the state as if it were dead.
|
|
State->UnionGroups(NewReg, 0);
|
|
RegRefs.erase(NewReg);
|
|
DefIndices[NewReg] = DefIndices[CurrReg];
|
|
KillIndices[NewReg] = KillIndices[CurrReg];
|
|
|
|
State->UnionGroups(CurrReg, 0);
|
|
RegRefs.erase(CurrReg);
|
|
DefIndices[CurrReg] = KillIndices[CurrReg];
|
|
KillIndices[CurrReg] = ~0u;
|
|
assert(((KillIndices[CurrReg] == ~0u) !=
|
|
(DefIndices[CurrReg] == ~0u)) &&
|
|
"Kill and Def maps aren't consistent for AntiDepReg!");
|
|
}
|
|
|
|
++Broken;
|
|
DEBUG(dbgs() << '\n');
|
|
}
|
|
}
|
|
}
|
|
|
|
ScanInstruction(MI, Count);
|
|
}
|
|
|
|
return Broken;
|
|
}
|