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a347f85dbe
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
986 B
Makefile
27 lines
986 B
Makefile
##===- lib/Target/ARM/Makefile -----------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file is distributed under the University of Illinois Open Source
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# License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = LLVMARMCodeGen
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TARGET = ARM
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \
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ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
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ARMGenInstrNames.inc ARMGenInstrInfo.inc \
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ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
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ARMGenDAGISel.inc ARMGenSubtarget.inc \
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ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
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ARMGenDecoderTables.inc ARMGenEDInfo.inc \
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ARMGenFastISel.inc ARMGenMCCodeEmitter.inc
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DIRS = InstPrinter AsmParser Disassembler TargetInfo
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include $(LEVEL)/Makefile.common
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