mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-06 09:54:49 +00:00
d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
164 lines
6.3 KiB
Python
Executable File
164 lines
6.3 KiB
Python
Executable File
#!/usr/bin/env python
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##===- generate-register-td.py --------------------------------*-python-*--===##
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##
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## The LLVM Compiler Infrastructure
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##
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## This file is distributed under the University of Illinois Open Source
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## License. See LICENSE.TXT for details.
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##
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##===----------------------------------------------------------------------===##
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##
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## This file describes the PTX register file generator.
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##
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##===----------------------------------------------------------------------===##
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from sys import argv, exit, stdout
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if len(argv) != 5:
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print('Usage: generate-register-td.py <num_preds> <num_16> <num_32> <num_64>')
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exit(1)
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try:
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num_pred = int(argv[1])
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num_16bit = int(argv[2])
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num_32bit = int(argv[3])
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num_64bit = int(argv[4])
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except:
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print('ERROR: Invalid integer parameter')
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exit(1)
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## Print the register definition file
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td_file = open('PTXRegisterInfo.td', 'w')
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td_file.write('''
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//===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the PTX register file
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//===----------------------------------------------------------------------===//
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class PTXReg<string n> : Register<n> {
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let Namespace = "PTX";
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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''')
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# Print predicate registers
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td_file.write('\n///===- Predicate Registers -----------------------------------------------===//\n\n')
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for r in range(0, num_pred):
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td_file.write('def P%d : PTXReg<"p%d">;\n' % (r, r))
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# Print 16-bit registers
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td_file.write('\n///===- 16-Bit Registers --------------------------------------------------===//\n\n')
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for r in range(0, num_16bit):
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td_file.write('def RH%d : PTXReg<"rh%d">;\n' % (r, r))
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# Print 32-bit registers
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td_file.write('\n///===- 32-Bit Registers --------------------------------------------------===//\n\n')
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for r in range(0, num_32bit):
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td_file.write('def R%d : PTXReg<"r%d">;\n' % (r, r))
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# Print 64-bit registers
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td_file.write('\n///===- 64-Bit Registers --------------------------------------------------===//\n\n')
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for r in range(0, num_64bit):
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td_file.write('def RD%d : PTXReg<"rd%d">;\n' % (r, r))
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td_file.write('''
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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''')
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# Print register classes
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td_file.write('def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%%u", 0, %d)>;\n' % (num_pred-1))
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td_file.write('def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%%u", 0, %d)>;\n' % (num_16bit-1))
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td_file.write('def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
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td_file.write('def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
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td_file.write('def RegF32 : RegisterClass<"PTX", [f32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
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td_file.write('def RegF64 : RegisterClass<"PTX", [f64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
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td_file.close()
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## Now write the PTXCallingConv.td file
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td_file = open('PTXCallingConv.td', 'w')
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# Reserve 10% of the available registers for return values, and the other 90%
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# for parameters
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num_ret_pred = int(0.1 * num_pred)
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num_ret_16bit = int(0.1 * num_16bit)
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num_ret_32bit = int(0.1 * num_32bit)
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num_ret_64bit = int(0.1 * num_64bit)
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num_param_pred = num_pred - num_ret_pred
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num_param_16bit = num_16bit - num_ret_16bit
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num_param_32bit = num_32bit - num_ret_32bit
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num_param_64bit = num_64bit - num_ret_64bit
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param_regs_pred = [('P%d' % (i+num_ret_pred)) for i in range(0, num_param_pred)]
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ret_regs_pred = ['P%d' % i for i in range(0, num_ret_pred)]
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param_regs_16bit = [('RH%d' % (i+num_ret_16bit)) for i in range(0, num_param_16bit)]
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ret_regs_16bit = ['RH%d' % i for i in range(0, num_ret_16bit)]
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param_regs_32bit = [('R%d' % (i+num_ret_32bit)) for i in range(0, num_param_32bit)]
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ret_regs_32bit = ['R%d' % i for i in range(0, num_ret_32bit)]
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param_regs_64bit = [('RD%d' % (i+num_ret_64bit)) for i in range(0, num_param_64bit)]
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ret_regs_64bit = ['RD%d' % i for i in range(0, num_ret_64bit)]
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param_list_pred = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_pred)
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ret_list_pred = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_pred)
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param_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_16bit)
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ret_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_16bit)
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param_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_32bit)
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ret_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_32bit)
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param_list_64bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_64bit)
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ret_list_64bit = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_64bit)
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td_file.write('''
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//===--- PTXCallingConv.td - Calling Conventions -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the PTX architecture.
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//
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//===----------------------------------------------------------------------===//
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// PTX Formal Parameter Calling Convention
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def CC_PTX : CallingConv<[
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CCIfType<[i1], CCAssignToReg<[%s]>>,
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CCIfType<[i16], CCAssignToReg<[%s]>>,
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CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
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CCIfType<[i64,f64], CCAssignToReg<[%s]>>
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]>;
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// PTX Return Value Calling Convention
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def RetCC_PTX : CallingConv<[
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CCIfType<[i1], CCAssignToReg<[%s]>>,
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CCIfType<[i16], CCAssignToReg<[%s]>>,
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CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
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CCIfType<[i64,f64], CCAssignToReg<[%s]>>
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]>;
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''' % (param_list_pred, param_list_16bit, param_list_32bit, param_list_64bit,
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ret_list_pred, ret_list_16bit, ret_list_32bit, ret_list_64bit))
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td_file.close()
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