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443838d8aa
The successors cache is now a local variable, making it more visible that it is only valid for the MBB being processed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239807 91177308-0d34-0410-b5e6-96231b3b80d8
813 lines
30 KiB
C++
813 lines
30 KiB
C++
//===-- MachineSink.cpp - Sinking for machine instructions ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass moves instructions into successor blocks when possible, so that
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// they aren't executed on paths where their results aren't needed.
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//
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// This pass is not intended to be a replacement or a complete alternative
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// for an LLVM-IR-level sinking pass. It is only designed to sink simple
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// constructs that are not exposed before lowering and instruction selection.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SparseBitVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "machine-sink"
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static cl::opt<bool>
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SplitEdges("machine-sink-split",
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cl::desc("Split critical edges during machine sinking"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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UseBlockFreqInfo("machine-sink-bfi",
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cl::desc("Use block frequency info to find successors to sink"),
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cl::init(true), cl::Hidden);
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STATISTIC(NumSunk, "Number of machine instructions sunk");
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STATISTIC(NumSplit, "Number of critical edges split");
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STATISTIC(NumCoalesces, "Number of copies coalesced");
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namespace {
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class MachineSinking : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI; // Machine register information
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MachineDominatorTree *DT; // Machine dominator tree
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MachinePostDominatorTree *PDT; // Machine post dominator tree
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MachineLoopInfo *LI;
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const MachineBlockFrequencyInfo *MBFI;
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AliasAnalysis *AA;
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// Remember which edges have been considered for breaking.
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SmallSet<std::pair<MachineBasicBlock*,MachineBasicBlock*>, 8>
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CEBCandidates;
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// Remember which edges we are about to split.
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// This is different from CEBCandidates since those edges
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// will be split.
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SetVector<std::pair<MachineBasicBlock*,MachineBasicBlock*> > ToSplit;
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SparseBitVector<> RegsToClearKillFlags;
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typedef std::map<MachineBasicBlock *, SmallVector<MachineBasicBlock *, 4>>
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AllSuccsCache;
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public:
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static char ID; // Pass identification
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MachineSinking() : MachineFunctionPass(ID) {
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initializeMachineSinkingPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachinePostDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addPreserved<MachinePostDominatorTree>();
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AU.addPreserved<MachineLoopInfo>();
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if (UseBlockFreqInfo)
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AU.addRequired<MachineBlockFrequencyInfo>();
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}
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void releaseMemory() override {
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CEBCandidates.clear();
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}
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private:
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bool ProcessBlock(MachineBasicBlock &MBB);
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bool isWorthBreakingCriticalEdge(MachineInstr *MI,
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MachineBasicBlock *From,
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MachineBasicBlock *To);
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/// \brief Postpone the splitting of the given critical
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/// edge (\p From, \p To).
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///
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/// We do not split the edges on the fly. Indeed, this invalidates
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/// the dominance information and thus triggers a lot of updates
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/// of that information underneath.
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/// Instead, we postpone all the splits after each iteration of
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/// the main loop. That way, the information is at least valid
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/// for the lifetime of an iteration.
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///
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/// \return True if the edge is marked as toSplit, false otherwise.
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/// False can be returned if, for instance, this is not profitable.
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bool PostponeSplitCriticalEdge(MachineInstr *MI,
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MachineBasicBlock *From,
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MachineBasicBlock *To,
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bool BreakPHIEdge);
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bool SinkInstruction(MachineInstr *MI, bool &SawStore,
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AllSuccsCache &AllSuccessors);
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bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
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MachineBasicBlock *DefMBB,
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bool &BreakPHIEdge, bool &LocalUse) const;
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MachineBasicBlock *FindSuccToSinkTo(MachineInstr *MI, MachineBasicBlock *MBB,
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bool &BreakPHIEdge, AllSuccsCache &AllSuccessors);
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bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
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MachineBasicBlock *MBB,
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MachineBasicBlock *SuccToSinkTo,
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AllSuccsCache &AllSuccessors);
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bool PerformTrivialForwardCoalescing(MachineInstr *MI,
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MachineBasicBlock *MBB);
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SmallVector<MachineBasicBlock *, 4> &
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GetAllSortedSuccessors(MachineInstr *MI, MachineBasicBlock *MBB,
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AllSuccsCache &AllSuccessors) const;
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};
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} // end anonymous namespace
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char MachineSinking::ID = 0;
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char &llvm::MachineSinkingID = MachineSinking::ID;
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INITIALIZE_PASS_BEGIN(MachineSinking, "machine-sink",
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"Machine code sinking", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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INITIALIZE_PASS_END(MachineSinking, "machine-sink",
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"Machine code sinking", false, false)
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bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr *MI,
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MachineBasicBlock *MBB) {
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if (!MI->isCopy())
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return false;
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned DstReg = MI->getOperand(0).getReg();
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if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
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!TargetRegisterInfo::isVirtualRegister(DstReg) ||
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!MRI->hasOneNonDBGUse(SrcReg))
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return false;
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const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
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const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
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if (SRC != DRC)
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return false;
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MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
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if (DefMI->isCopyLike())
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return false;
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DEBUG(dbgs() << "Coalescing: " << *DefMI);
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DEBUG(dbgs() << "*** to: " << *MI);
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MRI->replaceRegWith(DstReg, SrcReg);
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MI->eraseFromParent();
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// Conservatively, clear any kill flags, since it's possible that they are no
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// longer correct.
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MRI->clearKillFlags(SrcReg);
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++NumCoalesces;
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return true;
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}
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/// AllUsesDominatedByBlock - Return true if all uses of the specified register
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/// occur in blocks dominated by the specified block. If any use is in the
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/// definition block, then return false since it is never legal to move def
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/// after uses.
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bool
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MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
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MachineBasicBlock *MBB,
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MachineBasicBlock *DefMBB,
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bool &BreakPHIEdge,
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bool &LocalUse) const {
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assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
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"Only makes sense for vregs");
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// Ignore debug uses because debug info doesn't affect the code.
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if (MRI->use_nodbg_empty(Reg))
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return true;
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// BreakPHIEdge is true if all the uses are in the successor MBB being sunken
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// into and they are all PHI nodes. In this case, machine-sink must break
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// the critical edge first. e.g.
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//
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// BB#1: derived from LLVM BB %bb4.preheader
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// Predecessors according to CFG: BB#0
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// ...
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// %reg16385<def> = DEC64_32r %reg16437, %EFLAGS<imp-def,dead>
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// ...
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// JE_4 <BB#37>, %EFLAGS<imp-use>
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// Successors according to CFG: BB#37 BB#2
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//
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// BB#2: derived from LLVM BB %bb.nph
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// Predecessors according to CFG: BB#0 BB#1
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// %reg16386<def> = PHI %reg16434, <BB#0>, %reg16385, <BB#1>
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BreakPHIEdge = true;
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for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
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MachineInstr *UseInst = MO.getParent();
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unsigned OpNo = &MO - &UseInst->getOperand(0);
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MachineBasicBlock *UseBlock = UseInst->getParent();
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if (!(UseBlock == MBB && UseInst->isPHI() &&
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UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) {
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BreakPHIEdge = false;
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break;
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}
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}
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if (BreakPHIEdge)
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return true;
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for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
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// Determine the block of the use.
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MachineInstr *UseInst = MO.getParent();
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unsigned OpNo = &MO - &UseInst->getOperand(0);
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MachineBasicBlock *UseBlock = UseInst->getParent();
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if (UseInst->isPHI()) {
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// PHI nodes use the operand in the predecessor block, not the block with
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// the PHI.
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UseBlock = UseInst->getOperand(OpNo+1).getMBB();
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} else if (UseBlock == DefMBB) {
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LocalUse = true;
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return false;
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}
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// Check that it dominates.
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if (!DT->dominates(MBB, UseBlock))
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return false;
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}
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return true;
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}
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bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
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if (skipOptnoneFunction(*MF.getFunction()))
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return false;
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DEBUG(dbgs() << "******** Machine Sinking ********\n");
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TII = MF.getSubtarget().getInstrInfo();
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TRI = MF.getSubtarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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DT = &getAnalysis<MachineDominatorTree>();
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PDT = &getAnalysis<MachinePostDominatorTree>();
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LI = &getAnalysis<MachineLoopInfo>();
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MBFI = UseBlockFreqInfo ? &getAnalysis<MachineBlockFrequencyInfo>() : nullptr;
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AA = &getAnalysis<AliasAnalysis>();
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bool EverMadeChange = false;
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while (1) {
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bool MadeChange = false;
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// Process all basic blocks.
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CEBCandidates.clear();
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ToSplit.clear();
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for (auto &MBB: MF)
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MadeChange |= ProcessBlock(MBB);
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// If we have anything we marked as toSplit, split it now.
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for (auto &Pair : ToSplit) {
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auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, this);
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if (NewSucc != nullptr) {
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DEBUG(dbgs() << " *** Splitting critical edge:"
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" BB#" << Pair.first->getNumber()
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<< " -- BB#" << NewSucc->getNumber()
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<< " -- BB#" << Pair.second->getNumber() << '\n');
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MadeChange = true;
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++NumSplit;
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} else
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DEBUG(dbgs() << " *** Not legal to break critical edge\n");
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}
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// If this iteration over the code changed anything, keep iterating.
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if (!MadeChange) break;
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EverMadeChange = true;
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}
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// Now clear any kill flags for recorded registers.
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for (auto I : RegsToClearKillFlags)
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MRI->clearKillFlags(I);
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RegsToClearKillFlags.clear();
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return EverMadeChange;
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}
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bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
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// Can't sink anything out of a block that has less than two successors.
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if (MBB.succ_size() <= 1 || MBB.empty()) return false;
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// Don't bother sinking code out of unreachable blocks. In addition to being
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// unprofitable, it can also lead to infinite looping, because in an
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// unreachable loop there may be nowhere to stop.
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if (!DT->isReachableFromEntry(&MBB)) return false;
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bool MadeChange = false;
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// Cache all successors, sorted by frequency info and loop depth.
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AllSuccsCache AllSuccessors;
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// Walk the basic block bottom-up. Remember if we saw a store.
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MachineBasicBlock::iterator I = MBB.end();
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--I;
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bool ProcessedBegin, SawStore = false;
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do {
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MachineInstr *MI = I; // The instruction to sink.
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// Predecrement I (if it's not begin) so that it isn't invalidated by
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// sinking.
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ProcessedBegin = I == MBB.begin();
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if (!ProcessedBegin)
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--I;
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if (MI->isDebugValue())
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continue;
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bool Joined = PerformTrivialForwardCoalescing(MI, &MBB);
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if (Joined) {
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MadeChange = true;
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continue;
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}
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if (SinkInstruction(MI, SawStore, AllSuccessors))
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++NumSunk, MadeChange = true;
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// If we just processed the first instruction in the block, we're done.
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} while (!ProcessedBegin);
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return MadeChange;
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}
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bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr *MI,
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MachineBasicBlock *From,
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MachineBasicBlock *To) {
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// FIXME: Need much better heuristics.
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// If the pass has already considered breaking this edge (during this pass
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// through the function), then let's go ahead and break it. This means
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// sinking multiple "cheap" instructions into the same block.
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if (!CEBCandidates.insert(std::make_pair(From, To)).second)
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return true;
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if (!MI->isCopy() && !TII->isAsCheapAsAMove(MI))
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return true;
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// MI is cheap, we probably don't want to break the critical edge for it.
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// However, if this would allow some definitions of its source operands
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// to be sunk then it's probably worth it.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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continue;
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// We don't move live definitions of physical registers,
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// so sinking their uses won't enable any opportunities.
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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// If this instruction is the only user of a virtual register,
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// check if breaking the edge will enable sinking
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// both this instruction and the defining instruction.
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if (MRI->hasOneNonDBGUse(Reg)) {
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// If the definition resides in same MBB,
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// claim it's likely we can sink these together.
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// If definition resides elsewhere, we aren't
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// blocking it from being sunk so don't break the edge.
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MachineInstr *DefMI = MRI->getVRegDef(Reg);
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if (DefMI->getParent() == MI->getParent())
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return true;
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}
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}
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return false;
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}
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bool MachineSinking::PostponeSplitCriticalEdge(MachineInstr *MI,
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MachineBasicBlock *FromBB,
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MachineBasicBlock *ToBB,
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bool BreakPHIEdge) {
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if (!isWorthBreakingCriticalEdge(MI, FromBB, ToBB))
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return false;
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// Avoid breaking back edge. From == To means backedge for single BB loop.
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if (!SplitEdges || FromBB == ToBB)
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return false;
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// Check for backedges of more "complex" loops.
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if (LI->getLoopFor(FromBB) == LI->getLoopFor(ToBB) &&
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LI->isLoopHeader(ToBB))
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return false;
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// It's not always legal to break critical edges and sink the computation
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// to the edge.
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//
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// BB#1:
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// v1024
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// Beq BB#3
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// <fallthrough>
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// BB#2:
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// ... no uses of v1024
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// <fallthrough>
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// BB#3:
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// ...
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// = v1024
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//
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// If BB#1 -> BB#3 edge is broken and computation of v1024 is inserted:
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//
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// BB#1:
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// ...
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// Bne BB#2
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// BB#4:
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// v1024 =
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// B BB#3
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// BB#2:
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// ... no uses of v1024
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// <fallthrough>
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// BB#3:
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// ...
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// = v1024
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//
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// This is incorrect since v1024 is not computed along the BB#1->BB#2->BB#3
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// flow. We need to ensure the new basic block where the computation is
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// sunk to dominates all the uses.
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// It's only legal to break critical edge and sink the computation to the
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// new block if all the predecessors of "To", except for "From", are
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// not dominated by "From". Given SSA property, this means these
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// predecessors are dominated by "To".
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//
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// There is no need to do this check if all the uses are PHI nodes. PHI
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// sources are only defined on the specific predecessor edges.
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if (!BreakPHIEdge) {
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for (MachineBasicBlock::pred_iterator PI = ToBB->pred_begin(),
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E = ToBB->pred_end(); PI != E; ++PI) {
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if (*PI == FromBB)
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continue;
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if (!DT->dominates(ToBB, *PI))
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return false;
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}
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}
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ToSplit.insert(std::make_pair(FromBB, ToBB));
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return true;
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}
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static bool AvoidsSinking(MachineInstr *MI, MachineRegisterInfo *MRI) {
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return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence();
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}
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/// collectDebgValues - Scan instructions following MI and collect any
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/// matching DBG_VALUEs.
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static void collectDebugValues(MachineInstr *MI,
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SmallVectorImpl<MachineInstr *> &DbgValues) {
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DbgValues.clear();
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if (!MI->getOperand(0).isReg())
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return;
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MachineBasicBlock::iterator DI = MI; ++DI;
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for (MachineBasicBlock::iterator DE = MI->getParent()->end();
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DI != DE; ++DI) {
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if (!DI->isDebugValue())
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return;
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if (DI->getOperand(0).isReg() &&
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DI->getOperand(0).getReg() == MI->getOperand(0).getReg())
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DbgValues.push_back(DI);
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}
|
|
}
|
|
|
|
/// isProfitableToSinkTo - Return true if it is profitable to sink MI.
|
|
bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
|
|
MachineBasicBlock *MBB,
|
|
MachineBasicBlock *SuccToSinkTo,
|
|
AllSuccsCache &AllSuccessors) {
|
|
assert (MI && "Invalid MachineInstr!");
|
|
assert (SuccToSinkTo && "Invalid SinkTo Candidate BB");
|
|
|
|
if (MBB == SuccToSinkTo)
|
|
return false;
|
|
|
|
// It is profitable if SuccToSinkTo does not post dominate current block.
|
|
if (!PDT->dominates(SuccToSinkTo, MBB))
|
|
return true;
|
|
|
|
// It is profitable to sink an instruction from a deeper loop to a shallower
|
|
// loop, even if the latter post-dominates the former (PR21115).
|
|
if (LI->getLoopDepth(MBB) > LI->getLoopDepth(SuccToSinkTo))
|
|
return true;
|
|
|
|
// Check if only use in post dominated block is PHI instruction.
|
|
bool NonPHIUse = false;
|
|
for (MachineInstr &UseInst : MRI->use_nodbg_instructions(Reg)) {
|
|
MachineBasicBlock *UseBlock = UseInst.getParent();
|
|
if (UseBlock == SuccToSinkTo && !UseInst.isPHI())
|
|
NonPHIUse = true;
|
|
}
|
|
if (!NonPHIUse)
|
|
return true;
|
|
|
|
// If SuccToSinkTo post dominates then also it may be profitable if MI
|
|
// can further profitably sinked into another block in next round.
|
|
bool BreakPHIEdge = false;
|
|
// FIXME - If finding successor is compile time expensive then cache results.
|
|
if (MachineBasicBlock *MBB2 =
|
|
FindSuccToSinkTo(MI, SuccToSinkTo, BreakPHIEdge, AllSuccessors))
|
|
return isProfitableToSinkTo(Reg, MI, SuccToSinkTo, MBB2, AllSuccessors);
|
|
|
|
// If SuccToSinkTo is final destination and it is a post dominator of current
|
|
// block then it is not profitable to sink MI into SuccToSinkTo block.
|
|
return false;
|
|
}
|
|
|
|
/// Get the sorted sequence of successors for this MachineBasicBlock, possibly
|
|
/// computing it if it was not already cached.
|
|
SmallVector<MachineBasicBlock *, 4> &
|
|
MachineSinking::GetAllSortedSuccessors(MachineInstr *MI, MachineBasicBlock *MBB,
|
|
AllSuccsCache &AllSuccessors) const {
|
|
|
|
// Do we have the sorted successors in cache ?
|
|
auto Succs = AllSuccessors.find(MBB);
|
|
if (Succs != AllSuccessors.end())
|
|
return Succs->second;
|
|
|
|
SmallVector<MachineBasicBlock *, 4> AllSuccs(MBB->succ_begin(),
|
|
MBB->succ_end());
|
|
|
|
// Handle cases where sinking can happen but where the sink point isn't a
|
|
// successor. For example:
|
|
//
|
|
// x = computation
|
|
// if () {} else {}
|
|
// use x
|
|
//
|
|
const std::vector<MachineDomTreeNode *> &Children =
|
|
DT->getNode(MBB)->getChildren();
|
|
for (const auto &DTChild : Children)
|
|
// DomTree children of MBB that have MBB as immediate dominator are added.
|
|
if (DTChild->getIDom()->getBlock() == MI->getParent() &&
|
|
// Skip MBBs already added to the AllSuccs vector above.
|
|
!MBB->isSuccessor(DTChild->getBlock()))
|
|
AllSuccs.push_back(DTChild->getBlock());
|
|
|
|
// Sort Successors according to their loop depth or block frequency info.
|
|
std::stable_sort(
|
|
AllSuccs.begin(), AllSuccs.end(),
|
|
[this](const MachineBasicBlock *L, const MachineBasicBlock *R) {
|
|
uint64_t LHSFreq = MBFI ? MBFI->getBlockFreq(L).getFrequency() : 0;
|
|
uint64_t RHSFreq = MBFI ? MBFI->getBlockFreq(R).getFrequency() : 0;
|
|
bool HasBlockFreq = LHSFreq != 0 && RHSFreq != 0;
|
|
return HasBlockFreq ? LHSFreq < RHSFreq
|
|
: LI->getLoopDepth(L) < LI->getLoopDepth(R);
|
|
});
|
|
|
|
auto it = AllSuccessors.insert(std::make_pair(MBB, AllSuccs));
|
|
|
|
return it.first->second;
|
|
}
|
|
|
|
/// FindSuccToSinkTo - Find a successor to sink this instruction to.
|
|
MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI,
|
|
MachineBasicBlock *MBB,
|
|
bool &BreakPHIEdge,
|
|
AllSuccsCache &AllSuccessors) {
|
|
|
|
assert (MI && "Invalid MachineInstr!");
|
|
assert (MBB && "Invalid MachineBasicBlock!");
|
|
|
|
// Loop over all the operands of the specified instruction. If there is
|
|
// anything we can't handle, bail out.
|
|
|
|
// SuccToSinkTo - This is the successor to sink this instruction to, once we
|
|
// decide.
|
|
MachineBasicBlock *SuccToSinkTo = nullptr;
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue; // Ignore non-register operands.
|
|
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
if (MO.isUse()) {
|
|
// If the physreg has no defs anywhere, it's just an ambient register
|
|
// and we can freely move its uses. Alternatively, if it's allocatable,
|
|
// it could get allocated to something with a def during allocation.
|
|
if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
|
|
return nullptr;
|
|
} else if (!MO.isDead()) {
|
|
// A def that isn't dead. We can't move it.
|
|
return nullptr;
|
|
}
|
|
} else {
|
|
// Virtual register uses are always safe to sink.
|
|
if (MO.isUse()) continue;
|
|
|
|
// If it's not safe to move defs of the register class, then abort.
|
|
if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
|
|
return nullptr;
|
|
|
|
// Virtual register defs can only be sunk if all their uses are in blocks
|
|
// dominated by one of the successors.
|
|
if (SuccToSinkTo) {
|
|
// If a previous operand picked a block to sink to, then this operand
|
|
// must be sinkable to the same block.
|
|
bool LocalUse = false;
|
|
if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo, MBB,
|
|
BreakPHIEdge, LocalUse))
|
|
return nullptr;
|
|
|
|
continue;
|
|
}
|
|
|
|
// Otherwise, we should look at all the successors and decide which one
|
|
// we should sink to. If we have reliable block frequency information
|
|
// (frequency != 0) available, give successors with smaller frequencies
|
|
// higher priority, otherwise prioritize smaller loop depths.
|
|
for (MachineBasicBlock *SuccBlock :
|
|
GetAllSortedSuccessors(MI, MBB, AllSuccessors)) {
|
|
bool LocalUse = false;
|
|
if (AllUsesDominatedByBlock(Reg, SuccBlock, MBB,
|
|
BreakPHIEdge, LocalUse)) {
|
|
SuccToSinkTo = SuccBlock;
|
|
break;
|
|
}
|
|
if (LocalUse)
|
|
// Def is used locally, it's never safe to move this def.
|
|
return nullptr;
|
|
}
|
|
|
|
// If we couldn't find a block to sink to, ignore this instruction.
|
|
if (!SuccToSinkTo)
|
|
return nullptr;
|
|
if (!isProfitableToSinkTo(Reg, MI, MBB, SuccToSinkTo, AllSuccessors))
|
|
return nullptr;
|
|
}
|
|
}
|
|
|
|
// It is not possible to sink an instruction into its own block. This can
|
|
// happen with loops.
|
|
if (MBB == SuccToSinkTo)
|
|
return nullptr;
|
|
|
|
// It's not safe to sink instructions to EH landing pad. Control flow into
|
|
// landing pad is implicitly defined.
|
|
if (SuccToSinkTo && SuccToSinkTo->isLandingPad())
|
|
return nullptr;
|
|
|
|
return SuccToSinkTo;
|
|
}
|
|
|
|
/// SinkInstruction - Determine whether it is safe to sink the specified machine
|
|
/// instruction out of its current block into a successor.
|
|
bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore,
|
|
AllSuccsCache &AllSuccessors) {
|
|
// Don't sink insert_subreg, subreg_to_reg, reg_sequence. These are meant to
|
|
// be close to the source to make it easier to coalesce.
|
|
if (AvoidsSinking(MI, MRI))
|
|
return false;
|
|
|
|
// Check if it's safe to move the instruction.
|
|
if (!MI->isSafeToMove(AA, SawStore))
|
|
return false;
|
|
|
|
// Convergent operations may only be moved to control equivalent locations.
|
|
if (MI->isConvergent())
|
|
return false;
|
|
|
|
// FIXME: This should include support for sinking instructions within the
|
|
// block they are currently in to shorten the live ranges. We often get
|
|
// instructions sunk into the top of a large block, but it would be better to
|
|
// also sink them down before their first use in the block. This xform has to
|
|
// be careful not to *increase* register pressure though, e.g. sinking
|
|
// "x = y + z" down if it kills y and z would increase the live ranges of y
|
|
// and z and only shrink the live range of x.
|
|
|
|
bool BreakPHIEdge = false;
|
|
MachineBasicBlock *ParentBlock = MI->getParent();
|
|
MachineBasicBlock *SuccToSinkTo =
|
|
FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge, AllSuccessors);
|
|
|
|
// If there are no outputs, it must have side-effects.
|
|
if (!SuccToSinkTo)
|
|
return false;
|
|
|
|
|
|
// If the instruction to move defines a dead physical register which is live
|
|
// when leaving the basic block, don't move it because it could turn into a
|
|
// "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
|
|
for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
|
|
const MachineOperand &MO = MI->getOperand(I);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
|
|
if (SuccToSinkTo->isLiveIn(Reg))
|
|
return false;
|
|
}
|
|
|
|
DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo);
|
|
|
|
// If the block has multiple predecessors, this is a critical edge.
|
|
// Decide if we can sink along it or need to break the edge.
|
|
if (SuccToSinkTo->pred_size() > 1) {
|
|
// We cannot sink a load across a critical edge - there may be stores in
|
|
// other code paths.
|
|
bool TryBreak = false;
|
|
bool store = true;
|
|
if (!MI->isSafeToMove(AA, store)) {
|
|
DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n");
|
|
TryBreak = true;
|
|
}
|
|
|
|
// We don't want to sink across a critical edge if we don't dominate the
|
|
// successor. We could be introducing calculations to new code paths.
|
|
if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) {
|
|
DEBUG(dbgs() << " *** NOTE: Critical edge found\n");
|
|
TryBreak = true;
|
|
}
|
|
|
|
// Don't sink instructions into a loop.
|
|
if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) {
|
|
DEBUG(dbgs() << " *** NOTE: Loop header found\n");
|
|
TryBreak = true;
|
|
}
|
|
|
|
// Otherwise we are OK with sinking along a critical edge.
|
|
if (!TryBreak)
|
|
DEBUG(dbgs() << "Sinking along critical edge.\n");
|
|
else {
|
|
// Mark this edge as to be split.
|
|
// If the edge can actually be split, the next iteration of the main loop
|
|
// will sink MI in the newly created block.
|
|
bool Status =
|
|
PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge);
|
|
if (!Status)
|
|
DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
|
|
"break critical edge\n");
|
|
// The instruction will not be sunk this time.
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (BreakPHIEdge) {
|
|
// BreakPHIEdge is true if all the uses are in the successor MBB being
|
|
// sunken into and they are all PHI nodes. In this case, machine-sink must
|
|
// break the critical edge first.
|
|
bool Status = PostponeSplitCriticalEdge(MI, ParentBlock,
|
|
SuccToSinkTo, BreakPHIEdge);
|
|
if (!Status)
|
|
DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
|
|
"break critical edge\n");
|
|
// The instruction will not be sunk this time.
|
|
return false;
|
|
}
|
|
|
|
// Determine where to insert into. Skip phi nodes.
|
|
MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin();
|
|
while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI())
|
|
++InsertPos;
|
|
|
|
// collect matching debug values.
|
|
SmallVector<MachineInstr *, 2> DbgValuesToSink;
|
|
collectDebugValues(MI, DbgValuesToSink);
|
|
|
|
// Move the instruction.
|
|
SuccToSinkTo->splice(InsertPos, ParentBlock, MI,
|
|
++MachineBasicBlock::iterator(MI));
|
|
|
|
// Move debug values.
|
|
for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(),
|
|
DBE = DbgValuesToSink.end(); DBI != DBE; ++DBI) {
|
|
MachineInstr *DbgMI = *DBI;
|
|
SuccToSinkTo->splice(InsertPos, ParentBlock, DbgMI,
|
|
++MachineBasicBlock::iterator(DbgMI));
|
|
}
|
|
|
|
// Conservatively, clear any kill flags, since it's possible that they are no
|
|
// longer correct.
|
|
// Note that we have to clear the kill flags for any register this instruction
|
|
// uses as we may sink over another instruction which currently kills the
|
|
// used registers.
|
|
for (MachineOperand &MO : MI->operands()) {
|
|
if (MO.isReg() && MO.isUse())
|
|
RegsToClearKillFlags.set(MO.getReg()); // Remember to clear kill flags.
|
|
}
|
|
|
|
return true;
|
|
}
|