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36c7472106
AArch64 does not have a CPSR register in the same way that AArch32 does. Most of its compiler-relevant roles have been taken over by the more specific NZCV register (representing just the flags set by normal instructions). Its system control functions still remain, but are now under the pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR instructions described in the reference manual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207645 91177308-0d34-0410-b5e6-96231b3b80d8
144 lines
5.9 KiB
C++
144 lines
5.9 KiB
C++
//===-- ARM64InstPrinter.h - Convert ARM64 MCInst to assembly syntax ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an ARM64 MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARM64INSTPRINTER_H
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#define ARM64INSTPRINTER_H
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#include "MCTargetDesc/ARM64MCTargetDesc.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace llvm {
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class MCOperand;
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class ARM64InstPrinter : public MCInstPrinter {
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public:
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ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
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void printRegName(raw_ostream &OS, unsigned RegNo) const override;
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// Autogenerated by tblgen.
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virtual void printInstruction(const MCInst *MI, raw_ostream &O);
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virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
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virtual StringRef getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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}
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static const char *getRegisterName(unsigned RegNo,
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unsigned AltIdx = ARM64::NoRegAltName);
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protected:
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bool printSysAlias(const MCInst *MI, raw_ostream &O);
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// Operand printers
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
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raw_ostream &O);
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template<int Amount>
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void printPostIncOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
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printPostIncOperand(MI, OpNo, Amount, O);
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}
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void printVRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSysCROperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printAddSubImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printLogicalImm32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printLogicalImm64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printShifter(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printShiftedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printDotCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printAlignedLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printAMIndexed(const MCInst *MI, unsigned OpNum, unsigned Scale,
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raw_ostream &O);
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void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
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raw_ostream &O);
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template<int BitWidth>
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void printAMIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printAMIndexed(MI, OpNum, BitWidth / 8, O);
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}
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template<int BitWidth>
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void printAMIndexedWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
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}
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void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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template<int Scale>
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void printImmScale(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O,
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unsigned Scale);
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template<int BitWidth>
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void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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printMemoryPostIndexed(MI, OpNum, O, BitWidth / 8);
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}
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void printMemoryRegOffset(const MCInst *MI, unsigned OpNum, raw_ostream &O,
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int LegalShiftAmt);
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template<int BitWidth>
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void printMemoryRegOffset(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printMemoryRegOffset(MI, OpNum, O, BitWidth / 8);
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}
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void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O,
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StringRef LayoutSuffix);
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/// Print a list of vector registers where the type suffix is implicit
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/// (i.e. attached to the instruction rather than the registers).
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void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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template <unsigned NumLanes, char LaneKind>
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void printTypedVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printAdrpLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printBarrierOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printSystemPStateField(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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};
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class ARM64AppleInstPrinter : public ARM64InstPrinter {
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public:
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ARM64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
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void printInstruction(const MCInst *MI, raw_ostream &O) override;
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bool printAliasInstr(const MCInst *MI, raw_ostream &O) override;
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StringRef getRegName(unsigned RegNo) const override {
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return getRegisterName(RegNo);
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}
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static const char *getRegisterName(unsigned RegNo,
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unsigned AltIdx = ARM64::NoRegAltName);
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};
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}
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#endif
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