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ed76ca720b
The default assumes that a 16-bit signed offset is used. LDS instruction use a 16-bit unsigned offset, so it wasn't being used in some cases where it was assumed a negative offset could be used. More should be done here, but first isLegalAddressingMode needs to gain an addressing mode argument. For now, copy most of the rest of the default implementation with the immediate offset change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215732 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
2.8 KiB
LLVM
61 lines
2.8 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() #0
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declare void @llvm.AMDGPU.barrier.local() #1
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; Function Attrs: nounwind
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; SI-LABEL: @signed_ds_offset_addressing_loop
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; SI: BB0_1:
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; SI: V_ADD_I32_e32 [[VADDR:v[0-9]+]],
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x0
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x4
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x80
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x84
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; SI-DAG: DS_READ_B32 v{{[0-9]+}}, [[VADDR]], 0x100
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; SI: S_ENDPGM
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define void @signed_ds_offset_addressing_loop(float addrspace(1)* noalias nocapture %out, float addrspace(3)* noalias nocapture readonly %lptr, i32 %n) #2 {
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entry:
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #0
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%mul = shl nsw i32 %x.i, 1
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%sum.03 = phi float [ 0.000000e+00, %entry ], [ %add13, %for.body ]
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%offset.02 = phi i32 [ %mul, %entry ], [ %add14, %for.body ]
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%k.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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tail call void @llvm.AMDGPU.barrier.local() #1
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%arrayidx = getelementptr inbounds float addrspace(3)* %lptr, i32 %offset.02
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%tmp = load float addrspace(3)* %arrayidx, align 4
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%add1 = add nsw i32 %offset.02, 1
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%arrayidx2 = getelementptr inbounds float addrspace(3)* %lptr, i32 %add1
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%tmp1 = load float addrspace(3)* %arrayidx2, align 4
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%add3 = add nsw i32 %offset.02, 32
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%arrayidx4 = getelementptr inbounds float addrspace(3)* %lptr, i32 %add3
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%tmp2 = load float addrspace(3)* %arrayidx4, align 4
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%add5 = add nsw i32 %offset.02, 33
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%arrayidx6 = getelementptr inbounds float addrspace(3)* %lptr, i32 %add5
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%tmp3 = load float addrspace(3)* %arrayidx6, align 4
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%add7 = add nsw i32 %offset.02, 64
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%arrayidx8 = getelementptr inbounds float addrspace(3)* %lptr, i32 %add7
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%tmp4 = load float addrspace(3)* %arrayidx8, align 4
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%add9 = fadd float %tmp, %tmp1
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%add10 = fadd float %add9, %tmp2
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%add11 = fadd float %add10, %tmp3
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%add12 = fadd float %add11, %tmp4
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%add13 = fadd float %sum.03, %add12
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%inc = add nsw i32 %k.01, 1
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%add14 = add nsw i32 %offset.02, 97
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%exitcond = icmp eq i32 %inc, 8
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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%tmp5 = sext i32 %x.i to i64
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%arrayidx15 = getelementptr inbounds float addrspace(1)* %out, i64 %tmp5
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store float %add13, float addrspace(1)* %arrayidx15, align 4
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { noduplicate nounwind }
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attributes #2 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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