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13f4476c55
This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215399 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.6 KiB
LLVM
42 lines
1.6 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() #1
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; FIXME: This currently doesn't do a great job of clustering the
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; loads, which end up with extra moves between them. Right now, it
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; seems the only things areLoadsFromSameBasePtr is accomplishing is
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; ordering the loads so that the lower address loads come first.
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; FUNC-LABEL: @cluster_global_arg_loads
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; SI-DAG: BUFFER_LOAD_DWORD [[REG0:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; SI-DAG: BUFFER_LOAD_DWORD [[REG1:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:0x4
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; SI: BUFFER_STORE_DWORD [[REG0]]
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; SI: BUFFER_STORE_DWORD [[REG1]]
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define void @cluster_global_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr) #0 {
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%load0 = load i32 addrspace(1)* %ptr, align 4
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%gep = getelementptr i32 addrspace(1)* %ptr, i32 1
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%load1 = load i32 addrspace(1)* %gep, align 4
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store i32 %load0, i32 addrspace(1)* %out0, align 4
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store i32 %load1, i32 addrspace(1)* %out1, align 4
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ret void
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}
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; Test for a crach in SIInstrInfo::areLoadsFromSameBasePtr() when checking
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; an MUBUF load which does not have a vaddr operand.
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; FUNC-LABEL: @same_base_ptr_crash
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; SI: BUFFER_LOAD_DWORD
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; SI: BUFFER_LOAD_DWORD
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define void @same_base_ptr_crash(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset) {
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entry:
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%out1 = getelementptr i32 addrspace(1)* %out, i32 %offset
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%tmp0 = load i32 addrspace(1)* %out
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%tmp1 = load i32 addrspace(1)* %out1
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%tmp2 = add i32 %tmp0, %tmp1
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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