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allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
167 lines
5.3 KiB
C++
167 lines
5.3 KiB
C++
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//===-- Mips16RegisterInfo.cpp - MIPS16 Register Information -== ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS16 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16RegisterInfo.h"
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#include "Mips16InstrInfo.h"
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#include "Mips.h"
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#include "Mips16InstrInfo.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/DebugInfo.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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Mips16RegisterInfo::Mips16RegisterInfo(const MipsSubtarget &ST,
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const Mips16InstrInfo &I)
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: MipsRegisterInfo(ST), TII(I) {}
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bool Mips16RegisterInfo::requiresRegisterScavenging
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(const MachineFunction &MF) const {
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return true;
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}
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bool Mips16RegisterInfo::requiresFrameIndexScavenging
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(const MachineFunction &MF) const {
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return true;
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}
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bool Mips16RegisterInfo::useFPForScavengingIndex
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(const MachineFunction &MF) const {
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return false;
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}
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bool Mips16RegisterInfo::saveScavengerRegister
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(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &UseMI,
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const TargetRegisterClass *RC,
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unsigned Reg) const {
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DebugLoc DL;
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TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
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TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
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return true;
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}
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// This function eliminate ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void Mips16RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (!TFI->hasReservedCallFrame(MF)) {
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int64_t Amount = I->getOperand(0).getImm();
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if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
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Amount = -Amount;
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const Mips16InstrInfo *II = static_cast<const Mips16InstrInfo*>(&TII);
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II->adjustStackPtr(Mips::SP, Amount, MBB, I);
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}
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MBB.erase(I);
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}
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void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
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unsigned OpNo, int FrameIndex,
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uint64_t StackSize,
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int64_t SPOffset) const {
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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int MinCSFI = 0;
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int MaxCSFI = -1;
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if (CSI.size()) {
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MinCSFI = CSI[0].getFrameIdx();
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MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
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}
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// The following stack frame objects are always
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// referenced relative to $sp:
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// 1. Outgoing arguments.
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// 2. Pointer to dynamically allocated stack space.
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// 3. Locations for callee-saved registers.
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// Everything else is referenced relative to whatever register
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// getFrameRegister() returns.
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unsigned FrameReg;
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if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)
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FrameReg = Mips::SP;
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else {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (TFI->hasFP(MF)) {
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FrameReg = Mips::S0;
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}
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else {
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if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
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FrameReg = MI.getOperand(OpNo+2).getReg();
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else
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FrameReg = Mips::SP;
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}
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}
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// Calculate final offset.
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// - There is no need to change the offset if the frame object
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// is one of the
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// following: an outgoing argument, pointer to a dynamically allocated
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// stack space or a $gp restore location,
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// - If the frame object is any of the following,
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// its offset must be adjusted
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// by adding the size of the stack:
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// incoming argument, callee-saved register location or local variable.
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int64_t Offset;
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bool IsKill = false;
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Offset = SPOffset + (int64_t)StackSize;
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Offset += MI.getOperand(OpNo + 1).getImm();
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DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
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if (!MI.isDebugValue() && ( ((FrameReg != Mips::SP) && !isInt<16>(Offset)) ||
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((FrameReg == Mips::SP) && !isInt<15>(Offset)) )) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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unsigned NewImm;
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FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
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Offset = SignExtend64<16>(NewImm);
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IsKill = true;
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}
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MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
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}
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