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9994b911f4
This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242727 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
2.9 KiB
C++
90 lines
2.9 KiB
C++
//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "HexagonGenRegisterInfo.inc"
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//
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// We try not to hard code the reserved registers in our code,
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// so the following two macros were defined. However, there
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// are still a few places that R11 and R10 are hard wired.
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// See below. If, in the future, we decided to change the reserved
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// register. Don't forget changing the following places.
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//
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// 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td
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// 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td
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// 3. the definition of "IntRegs" in HexagonRegisterInfo.td
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// 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td
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//
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#define HEXAGON_RESERVED_REG_1 Hexagon::R10
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#define HEXAGON_RESERVED_REG_2 Hexagon::R11
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namespace llvm {
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class HexagonRegisterInfo : public HexagonGenRegisterInfo {
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public:
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HexagonRegisterInfo();
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/// Code Generation virtual methods...
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
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const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
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/// Returns true since we may need scavenging for a temporary register
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/// when generating hardware loop instructions.
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bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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return true;
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}
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/// Returns true. Spill code for predicate registers might need an extra
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/// register.
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
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return true;
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}
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/// Returns true if the frame pointer is valid.
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bool useFPForScavengingIndex(const MachineFunction &MF) const override;
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
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return true;
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}
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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unsigned getFrameRegister() const;
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unsigned getStackRegister() const;
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const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF) const;
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unsigned getFirstCallerSavedNonParamReg() const;
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bool isEHReturnCalleeSaveReg(unsigned Reg) const;
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bool isCalleeSaveReg(unsigned Reg) const;
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};
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} // end namespace llvm
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#endif
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