mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
151 lines
4.5 KiB
LLVM
151 lines
4.5 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vsras8:
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;CHECK: ssra.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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%tmp4 = add <8 x i8> %tmp1, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vsras16:
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;CHECK: ssra.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
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%tmp4 = add <4 x i16> %tmp1, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vsras32:
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;CHECK: ssra.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 >
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%tmp4 = add <2 x i32> %tmp1, %tmp3
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vsraQs8:
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;CHECK: ssra.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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%tmp4 = add <16 x i8> %tmp1, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vsraQs16:
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;CHECK: ssra.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vsraQs32:
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;CHECK: ssra.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: vsraQs64:
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;CHECK: ssra.2d
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 >
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vsrau8:
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;CHECK: usra.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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%tmp4 = add <8 x i8> %tmp1, %tmp3
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vsrau16:
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;CHECK: usra.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
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%tmp4 = add <4 x i16> %tmp1, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vsrau32:
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;CHECK: usra.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 >
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%tmp4 = add <2 x i32> %tmp1, %tmp3
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vsraQu8:
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;CHECK: usra.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
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%tmp4 = add <16 x i8> %tmp1, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vsraQu16:
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;CHECK: usra.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
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%tmp4 = add <8 x i16> %tmp1, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vsraQu32:
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;CHECK: usra.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
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%tmp4 = add <4 x i32> %tmp1, %tmp3
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: vsraQu64:
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;CHECK: usra.2d
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 >
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%tmp4 = add <2 x i64> %tmp1, %tmp3
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ret <2 x i64> %tmp4
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}
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define <1 x i64> @vsra_v1i64(<1 x i64> %A, <1 x i64> %B) nounwind {
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; CHECK-LABEL: vsra_v1i64:
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; CHECK: ssra d0, d1, #63
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%tmp3 = ashr <1 x i64> %B, < i64 63 >
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%tmp4 = add <1 x i64> %A, %tmp3
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ret <1 x i64> %tmp4
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}
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