mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 18:31:04 +00:00
1d6373c1af
select. Also teach it that the bit count instructions can only set the low bits of the result, depending on the size of the input. This allows us to compile this: int %eq0(int %a) { %tmp.1 = seteq int %a, 0 ; <bool> [#uses=1] %tmp.2 = cast bool %tmp.1 to int ; <int> [#uses=1] ret int %tmp.2 } To this: _eq0: cntlzw r2, r3 srwi r3, r2, 5 blr instead of this: _eq0: cntlzw r2, r3 rlwinm r3, r2, 27, 31, 31 blr when setcc is marked illegal on ppc (which restores parity to non-illegal setcc). Thanks to Nate for pointing this out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23013 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
---|---|---|
.. | ||
SelectionDAG | ||
AsmPrinter.cpp | ||
BranchFolding.cpp | ||
ELFWriter.cpp | ||
IntrinsicLowering.cpp | ||
LiveInterval.cpp | ||
LiveInterval.h | ||
LiveIntervalAnalysis.cpp | ||
LiveIntervalAnalysis.h | ||
LiveVariables.cpp | ||
MachineBasicBlock.cpp | ||
MachineCodeEmitter.cpp | ||
MachineFunction.cpp | ||
MachineInstr.cpp | ||
Makefile | ||
Passes.cpp | ||
PHIElimination.cpp | ||
PhysRegTracker.h | ||
PrologEpilogInserter.cpp | ||
RegAllocIterativeScan.cpp | ||
RegAllocLinearScan.cpp | ||
RegAllocLocal.cpp | ||
RegAllocSimple.cpp | ||
TwoAddressInstructionPass.cpp | ||
UnreachableBlockElim.cpp | ||
VirtRegMap.cpp | ||
VirtRegMap.h |