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b58f498f75
a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
368 lines
12 KiB
C++
368 lines
12 KiB
C++
//===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MSP430 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "msp430-reg-info"
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#include "MSP430.h"
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#include "MSP430MachineFunctionInfo.h"
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#include "MSP430RegisterInfo.h"
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#include "MSP430TargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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// FIXME: Provide proper call frame setup / destroy opcodes.
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MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
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const TargetInstrInfo &tii)
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: MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
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TM(tm), TII(tii) {
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StackAlign = TM.getFrameInfo()->getStackAlignment();
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}
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const unsigned*
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MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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static const unsigned CalleeSavedRegs[] = {
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MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
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MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
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0
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};
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return CalleeSavedRegs;
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}
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const TargetRegisterClass *const *
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MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
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&MSP430::GR16RegClass, &MSP430::GR16RegClass,
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&MSP430::GR16RegClass, &MSP430::GR16RegClass,
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&MSP430::GR16RegClass, &MSP430::GR16RegClass,
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&MSP430::GR16RegClass, &MSP430::GR16RegClass,
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0
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};
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return CalleeSavedRegClasses;
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}
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BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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// Mark 4 special registers as reserved.
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Reserved.set(MSP430::PCW);
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Reserved.set(MSP430::SPW);
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Reserved.set(MSP430::SRW);
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Reserved.set(MSP430::CGW);
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// Mark frame pointer as reserved if needed.
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if (hasFP(MF))
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Reserved.set(MSP430::FPW);
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return Reserved;
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}
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const TargetRegisterClass *
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MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
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return &MSP430::GR16RegClass;
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}
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bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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bool MSP430RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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void MSP430RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (!hasReservedCallFrame(MF)) {
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// If the stack pointer can be changed after prologue, turn the
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// adjcallstackup instruction into a 'sub SPW, <amt>' and the
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// adjcallstackdown instruction into 'add SPW, <amt>'
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// TODO: consider using push / pop instead of sub + store / add
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MachineInstr *Old = I;
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uint64_t Amount = Old->getOperand(0).getImm();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
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MachineInstr *New = 0;
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if (Old->getOpcode() == getCallFrameSetupOpcode()) {
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New = BuildMI(MF, Old->getDebugLoc(),
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TII.get(MSP430::SUB16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(Amount);
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} else {
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assert(Old->getOpcode() == getCallFrameDestroyOpcode());
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// factor out the amount the callee already popped.
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uint64_t CalleeAmt = Old->getOperand(1).getImm();
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Amount -= CalleeAmt;
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if (Amount)
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New = BuildMI(MF, Old->getDebugLoc(),
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TII.get(MSP430::ADD16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(Amount);
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}
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if (New) {
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// The SRW implicit def is dead.
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New->getOperand(3).setIsDead();
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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} else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
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// If we are performing frame pointer elimination and if the callee pops
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// something off the stack pointer, add it back.
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if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
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MachineInstr *Old = I;
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MachineInstr *New =
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BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
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MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
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// The SRW implicit def is dead.
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New->getOperand(3).setIsDead();
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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unsigned
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MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, int *Value,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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DebugLoc dl = MI.getDebugLoc();
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getIndex();
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unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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// Skip the saved PC
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Offset += 2;
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if (!hasFP(MF))
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Offset += MF.getFrameInfo()->getStackSize();
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else
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Offset += 2; // Skip the saved FPW
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// Fold imm into offset
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Offset += MI.getOperand(i+1).getImm();
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if (MI.getOpcode() == MSP430::ADD16ri) {
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// This is actually "load effective address" of the stack slot
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// instruction. We have only two-address instructions, thus we need to
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// expand it into mov + add
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MI.setDesc(TII.get(MSP430::MOV16rr));
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MI.getOperand(i).ChangeToRegister(BasePtr, false);
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if (Offset == 0)
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return 0;
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// We need to materialize the offset via add instruction.
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unsigned DstReg = MI.getOperand(0).getReg();
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if (Offset < 0)
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BuildMI(MBB, next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
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.addReg(DstReg).addImm(-Offset);
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else
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BuildMI(MBB, next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
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.addReg(DstReg).addImm(Offset);
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return 0;
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}
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MI.getOperand(i).ChangeToRegister(BasePtr, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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return 0;
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}
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void
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MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
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const {
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// Create a frame entry for the FPW register that must be saved.
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if (hasFP(MF)) {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4);
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assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
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"Slot for FPW register must be last in order to be found!");
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FrameIdx = 0;
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}
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}
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void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
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DebugLoc::getUnknownLoc());
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// Get the number of bytes to allocate from the FrameInfo.
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uint64_t StackSize = MFI->getStackSize();
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uint64_t NumBytes = 0;
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if (hasFP(MF)) {
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// Calculate required stack adjustment
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uint64_t FrameSize = StackSize - 2;
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NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
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// Get the offset of the stack slot for the EBP register... which is
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// guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
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// Update the frame offset adjustment.
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MFI->setOffsetAdjustment(-NumBytes);
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// Save FPW into the appropriate stack slot...
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
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.addReg(MSP430::FPW, RegState::Kill);
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// Update FPW with the new base value...
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
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.addReg(MSP430::SPW);
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// Mark the FramePtr as live-in in every block except the entry.
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for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
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I != E; ++I)
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I->addLiveIn(MSP430::FPW);
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} else
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NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
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// Skip the callee-saved push instructions.
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while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
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++MBBI;
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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if (NumBytes) { // adjust stack pointer: SPW -= numbytes
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// If there is an SUB16ri of SPW immediately before this instruction, merge
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// the two.
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//NumBytes -= mergeSPUpdates(MBB, MBBI, true);
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// If there is an ADD16ri or SUB16ri of SPW immediately after this
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// instruction, merge the two instructions.
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// mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
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if (NumBytes) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(NumBytes);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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}
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}
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void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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unsigned RetOpcode = MBBI->getOpcode();
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DebugLoc DL = MBBI->getDebugLoc();
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switch (RetOpcode) {
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case MSP430::RET: break; // These are ok
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default:
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llvm_unreachable("Can only insert epilog into returning blocks");
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}
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// Get the number of bytes to allocate from the FrameInfo
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uint64_t StackSize = MFI->getStackSize();
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unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
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uint64_t NumBytes = 0;
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if (hasFP(MF)) {
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// Calculate required stack adjustment
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uint64_t FrameSize = StackSize - 2;
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NumBytes = FrameSize - CSSize;
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// pop FPW.
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
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} else
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NumBytes = StackSize - CSSize;
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// Skip the callee-saved pop instructions.
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while (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PI = prior(MBBI);
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unsigned Opc = PI->getOpcode();
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if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
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break;
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--MBBI;
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}
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DL = MBBI->getDebugLoc();
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// If there is an ADD16ri or SUB16ri of SPW immediately before this
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// instruction, merge the two instructions.
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//if (NumBytes || MFI->hasVarSizedObjects())
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// mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
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if (MFI->hasVarSizedObjects()) {
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BuildMI(MBB, MBBI, DL,
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TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
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if (CSSize) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL,
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TII.get(MSP430::SUB16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(CSSize);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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} else {
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// adjust stack pointer back: SPW += numbytes
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if (NumBytes) {
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MachineInstr *MI =
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BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
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.addReg(MSP430::SPW).addImm(NumBytes);
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// The SRW implicit def is dead.
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MI->getOperand(3).setIsDead();
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}
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}
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}
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unsigned MSP430RegisterInfo::getRARegister() const {
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return MSP430::PCW;
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}
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unsigned MSP430RegisterInfo::getFrameRegister(MachineFunction &MF) const {
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return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
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}
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int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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llvm_unreachable("Not implemented yet!");
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return 0;
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}
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#include "MSP430GenRegisterInfo.inc"
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