mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-18 10:08:34 +00:00
699623d3b3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28655 91177308-0d34-0410-b5e6-96231b3b80d8
116 lines
2.3 KiB
Plaintext
116 lines
2.3 KiB
Plaintext
|
|
=pod
|
|
|
|
=head1 NAME
|
|
|
|
tblgen - Target Description To C++ Code Generator
|
|
|
|
=head1 SYNOPSIS
|
|
|
|
B<tblgen> [I<options>] [I<filename>]
|
|
|
|
=head1 DESCRIPTION
|
|
|
|
B<tblgen> translates from target description (.td) files into C++ code that can
|
|
be included in the definition of an LLVM target library. Most users of LLVM will
|
|
not need to use this program. It is only for assisting with writing an LLVM
|
|
target backend.
|
|
|
|
The input and output of B<tblgen> is beyond the scope of this short
|
|
introduction. Please see the I<CodeGeneration> page in the LLVM documentation.
|
|
|
|
The F<filename> argument specifies the name of a Target Description (.td) file
|
|
to read as input.
|
|
|
|
=head1 OPTIONS
|
|
|
|
=over
|
|
|
|
=item B<--help>
|
|
|
|
Print a summary of command line options.
|
|
|
|
=item B<-o> F<filename>
|
|
|
|
Specify the output file name. If F<filename> is C<->, then B<tblgen>
|
|
sends its output to standard output.
|
|
|
|
=item B<-I> F<directory>
|
|
|
|
Specify where to find other target description files for inclusion. The
|
|
F<directory> value should be a full or partial path to a directory that contains
|
|
target description files.
|
|
|
|
=item B<-asmwriternum> F<N>
|
|
|
|
Make -gen-asm-writer emit assembly writer number F<N>.
|
|
|
|
=item B<-class> F<class Name>
|
|
|
|
Print the enumeration list for this class.
|
|
|
|
=item B<-print-records>
|
|
|
|
Print all records to standard output (default).
|
|
|
|
=item B<-print-enums>
|
|
|
|
Print enumeration values for a class
|
|
|
|
=item B<-gen-emitter>
|
|
|
|
Generate machine code emitter.
|
|
|
|
=item B<-gen-register-enums>
|
|
|
|
Generate the enumeration values for all registers.
|
|
|
|
=item B<-gen-register-desc>
|
|
|
|
Generate a register info description for each register.
|
|
|
|
=item B<-gen-register-desc-header>
|
|
|
|
Generate a register info description header for each register.
|
|
|
|
=item B<-gen-instr-enums>
|
|
|
|
Generate enumeration values for instructions.
|
|
|
|
=item B<-gen-instr-desc>
|
|
|
|
Generate instruction descriptions.
|
|
|
|
=item B<-gen-asm-writer>
|
|
|
|
Generate the assembly writer.
|
|
|
|
=item B<-gen-dag-isel>
|
|
|
|
Generate a DAG (Directed Acycle Graph) instruction selector.
|
|
|
|
=item B<-gen-subtarget>
|
|
|
|
Generate subtarget enumerations.
|
|
|
|
=item B<-gen-intrinsic>
|
|
|
|
Generate intrinsic information.
|
|
|
|
=item B<-version>
|
|
|
|
Show the version number of this program.
|
|
|
|
=back
|
|
|
|
=head1 EXIT STATUS
|
|
|
|
If B<tblgen> succeeds, it will exit with 0. Otherwise, if an error
|
|
occurs, it will exit with a non-zero value.
|
|
|
|
=head1 AUTHORS
|
|
|
|
Maintained by The LLVM Team (L<http://llvm.org>).
|
|
|
|
=cut
|