Jim Grosbach a3edd6a038 AArch64: Better codegen for storing to __fp16. ... Storing will generally be immediately preceded by rounding from an f32 or f64, so make sure to match those patterns directly to convert into the FPR16 register class directly rather than going through the integer GPRs. This also eliminates an extra step in the convert-from-f64 path which was first converting to f32 and then to f16 from there. rdar://17594379 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212638 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-09 18:55:52 +00:00
..
AArch64	AArch64: Better codegen for storing to __fp16.	2014-07-09 18:55:52 +00:00
ARM	ARM: properly lower dllimport'ed global values	2014-07-07 05:18:35 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	Add a new attribute called 'jumptable' that creates jump-instruction tables for functions marked with this attribute.	2014-06-05 19:29:43 +00:00
Hexagon	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Inputs
Mips	[mips][mips64r6] Correct select patterns that have the condition or true/false values backwards	2014-07-09 10:47:26 +00:00
MSP430	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
NVPTX	[NVPTX] Add reflect intrinsic (better than matching by function name)	2014-06-27 18:36:11 +00:00
PowerPC	[PowerPC] Fix testcase regression	2014-07-07 19:41:54 +00:00
R600	R600: Fix mishandling of load / store chains.	2014-07-07 18:34:45 +00:00
SPARC	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	ARM: Fix fastcc calling convention for Thumb1	2014-06-13 08:33:03 +00:00
Thumb2	ARM: Fix TPsoft for Thumb mode	2014-06-24 15:45:59 +00:00
X86	[x86] Fix a bug in my new zext-vector-inreg DAG trickery where we were	2014-07-09 12:36:54 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00